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boards/platforms/arty: use 1.5V and the 16bits instead of only 8bits

This commit is contained in:
Florent Kermarrec 2016-04-26 23:29:35 +02:00
parent e6681bbb9c
commit ab8569916b
1 changed files with 19 additions and 18 deletions
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37
litex/boards/platforms/arty.py
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@ -49,24 +49,25 @@ _io = [
Subsignal("a", Pins(
"R2 M6 N4 T1 N6 R7 V6 U7",
"R8 V7 R6 U6 T6 T8"),
IOStandard("SSTL135")),
Subsignal("ba", Pins("R1 P4 P2"), IOStandard("SSTL135")),
Subsignal("ras_n", Pins("P3"), IOStandard("SSTL135")),
Subsignal("cas_n", Pins("M4"), IOStandard("SSTL135")),
Subsignal("we_n", Pins("P5"), IOStandard("SSTL135")),
Subsignal("cs_n", Pins("U8"), IOStandard("SSTL135")),
Subsignal("dm", Pins("L1"), IOStandard("SSTL135")),
IOStandard("SSTL15")),
Subsignal("ba", Pins("R1 P4 P2"), IOStandard("SSTL15")),
Subsignal("ras_n", Pins("P3"), IOStandard("SSTL15")),
Subsignal("cas_n", Pins("M4"), IOStandard("SSTL15")),
Subsignal("we_n", Pins("P5"), IOStandard("SSTL15")),
Subsignal("cs_n", Pins("U8"), IOStandard("SSTL15")),
Subsignal("dm", Pins("L1 U1"), IOStandard("SSTL15")),
Subsignal("dq", Pins(
"K5 L3 K3 L6 M3 M1 L4 M2"),
IOStandard("SSTL135"),
Misc("IN_TERM=UNTUNED_SPLIT_50")),
Subsignal("dqs_p", Pins("N2"), IOStandard("DIFF_SSTL135")),
Subsignal("dqs_n", Pins("N1"), IOStandard("DIFF_SSTL135")),
Subsignal("clk_p", Pins("U9"), IOStandard("DIFF_SSTL135")),
Subsignal("clk_n", Pins("V9"), IOStandard("DIFF_SSTL135")),
Subsignal("cke", Pins("N5"), IOStandard("SSTL135")),
Subsignal("odt", Pins("R5"), IOStandard("SSTL135")),
Subsignal("reset_n", Pins("K6"), IOStandard("SSTL135")),
"K5 L3 K3 L6 M3 M1 L4 M2",
"V4 T5 U4 V5 V1 T3 U3 R3"),
IOStandard("SSTL15"),
Misc("IN_TERM=UNTUNED_SPLIT_40")),
Subsignal("dqs_p", Pins("N2 U2"), IOStandard("DIFF_SSTL15")),
Subsignal("dqs_n", Pins("N1 V2"), IOStandard("DIFF_SSTL15")),
Subsignal("clk_p", Pins("U9"), IOStandard("DIFF_SSTL15")),
Subsignal("clk_n", Pins("V9"), IOStandard("DIFF_SSTL15")),
Subsignal("cke", Pins("N5"), IOStandard("SSTL15")),
Subsignal("odt", Pins("R5"), IOStandard("SSTL15")),
Subsignal("reset_n", Pins("K6"), IOStandard("SSTL15")),
Misc("SLEW=FAST"),
),
@ -104,7 +105,7 @@ class Platform(XilinxPlatform):
["write_cfgmem -force -format bin -interface spix4 -size 16 "
"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
self.programmer = programmer
self.add_platform_command("set_property INTERNAL_VREF 0.675 [get_iobanks 34]")
self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]")
def create_programmer(self):
if self.programmer == "xc3sprog":