CHANGES.md: Update.
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Florent Kermarrec
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CHANGES.md
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CHANGES.md
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[> Changes since 2022.12
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------------------------
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[> Fixed
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--------
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- build/xilinx/vivado : Fixed Verilog include path.
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- builder/meson : Fixed version comparison.
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- liblitedram : Fixed write leveling with x4 modules.
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- integration/soc : Fixed alignment of origin on size.
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- litex_sim : Fixed ram_init.
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- libbase/i2c : Fixed various issues.
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- integration/soc : Fixed/Removed soc_region_cls workaround.
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- cores/gpio : Fixed IRQ generation.
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- litex_sim : Fixed --with-etherbone.
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- build/efinix : Fixed iface.py execution order.
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- cpu/Vex/NaxRiscv : Fixed IRQ numbering (0 reserved).
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- cpu/rocket : Fixed compilation with newer binutils.
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- cpu/soc : Fixed CPU IRQ reservation.
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- litepcie/software : Fixed compilation with DMA_CHECK_DATA commented.
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- litedram/dma : Fixed rdata connection (omit list update since LiteX AXI changes).
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[> Added
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--------
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- clock/intel : Added StratixVPLL.
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- cores/dma : Added FIFO on WishboneDMAReader to pipeline reads and allow bursting.
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- liblitedram : Improved SPD read with sdram_read_spd function.
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- bios/liblitedram : Added utils and used them to print memory sizes.
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- build/parser : Added a method to search default value for an argument.
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- litex_setup : Added Arch Linux RISC-V/OR1K/POWER-PC GCC toolchain install.
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- cores/pwm : Added reset signal (to allow external reset/synchronization).
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- cpu/cva6 : Updated.
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- cores/prbs : Improved timings.
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- litex_sim : Allowed enabling SDRAM BIST.
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- liblitedram : Refactored BIST functions and added sdram_hw_test.
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- soc/software : Added extern C (required to link with cpp code).
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- cpu/VexRiscv-SMP : Avoided silent generation failure.
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- cores/spi_flash : Added Ultrascale support.
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- clock/gowin_gw1n : Fixed simulation warnings.
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- liblitedram : Various improvements/cleanups.
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- cpu/Naxriscv : Exposed FPU parameter.
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- cores/xadc : Refactored/Cleaned up.
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- cores/dna : Added initial Ultrascale(+) support and reduced default clk_divider to 2.
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- cores/usb_ohci : Added support for multiple ports.
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- litex_cli : Added binary support for register dump.
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- cpu/NaxRiscv : Enabled FPU in crt0.S.
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- core/icap : Added initial Ultrascale(+) support and clk_divider parameter.
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- litex_sim : Added initial video support.
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- soc/add_video : Added framebuffer region definition.
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- litex_term : Avoided use of multiprocessing.
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- cores/esc : Added initial ESC core with DSHOT 150/300/600 support.
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- litex_json2dts : Allowed/Prepared Rocket support and made it more generic.
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- gen/common : Added Open/Unsigned/Signed signal definition and updated cores to use it.
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- global : Added initial list of sponsors/partners.
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- build/xilinx : Improved Xilinx US/US+ support.
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- build/platform : Added get_bitstream_extension method.
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- cpu/VexRiscvSMP : Added standard variant.
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- cpu/cva6 : Added 32-bit variant support and various improvements.
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- clock/gowin : Added GW2AR support.
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- build/efinix : Added option to select active/passive SPI mode.
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- cores/bitbang : Added documentation.
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- litex_term : Improved connection setup.
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- clock/gowin : Improved VCO config computation and added CLKOUTP/CLKOUTD/CLKOUTD3 support.
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- cpu/rocket : Reworked variants.
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- liblitesdcard : Avoided use of stop transmission for writes when only one block.
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- installation : Simplified/Improved ci.yml/MANIFEST.in/setup.py.
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- cores/pwm : Added MultiChannelPWM support.
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- soc/add_pcie : Exposed more DMA parameters.
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- litepcie/dma : Improved LitePCIeDMAStatus timings.
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- litepcie_gen : Exposed 64-bit support.
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- litepcie/dma : Better configuration decoupling between DMAWriter/Reader.
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- litepcie/dma : Allowed software to get DMA status.
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- litepcie/phy : Replaced Xilinx generated core on 7-series Verilog with Migen/LiteX code.
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- litepcie/msi : Improved MSI filtering.
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- litepcie_gen : Added MSI rate limiting on Ultrascale(+) to avoid stall issues.
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- liteiclink/prbs : Improved PRBS RX timings.
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- liteiclink/gty/gth : Added power-down signal on GTYQuadPLL and GTHQuadPLL.
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- litelclink/gty/gth : Integrated 7-series improvements.
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- litelclink/gty/gth : Added DRP interface on QuadPLL.
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- litedram/bist : Ensured proper completion of writes.
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- litedram/bist : Replicated data for large data-width.
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- litedram/ci : Allowed tests to run in parallel.
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- litedram/gw2ddrphy : Improvements to remove warnings in simulation.
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[> Changed
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----------
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- builder/export : Added soc-csv/-json/--svd arguments (in addition to csr-xy).
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- litepcie/phy : Retained only Gen3/4 support and removed Gen2.
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[> 2022.12, released on January 2th 2023
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----------------------------------------
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@ -21,7 +109,7 @@
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[> Added
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--------
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- soc : Add new "x" (executable) mode to SoCRegion.
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- cpu/NaRiscv : Update to latest and add parameters.
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- cpu/NaxRiscv : Update to latest and add parameters.
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- soc : Propagate address_width on dynamically created interfaces.
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- get_mem_data : Add data_width support.
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- cores/dma : Allow defining ready behavior on idle.
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