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interconnect/stream/ClockDomainCrossing: Expose buffered parameter.

This commit is contained in:
Florent Kermarrec 2022-10-06 18:30:02 +02:00
parent 75bf668883
commit ac3699770c
1 changed files with 2 additions and 2 deletions
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4
litex/soc/interconnect/stream.py
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@ -242,7 +242,7 @@ class AsyncFIFO(_FIFOWrapper):
# ClockDomainCrossing ------------------------------------------------------------------------------
class ClockDomainCrossing(Module):
def __init__(self, layout, cd_from="sys", cd_to="sys", depth=None, with_common_rst=False):
def __init__(self, layout, cd_from="sys", cd_to="sys", depth=None, buffered=False, with_common_rst=False):
self.sink = Endpoint(layout)
self.source = Endpoint(layout)
@ -275,7 +275,7 @@ class ClockDomainCrossing(Module):
]
# Add Asynchronous FIFO
cdc = AsyncFIFO(layout, depth)
cdc = AsyncFIFO(layout, depth, buffered=buffered)
cdc = ClockDomainsRenamer({"write": cd_from, "read": cd_to})(cdc)
self.submodules += cdc