Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

boards/plaforms: add FMC LPC connector to nexys_video

This commit is contained in:
Florent Kermarrec 2017-02-16 19:16:07 +01:00
parent afd0a0c7f3
commit ac70083453
1 changed files with 80 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

81
litex/boards/platforms/nexys_video.py
View File

@ -125,13 +125,92 @@ _io = [
),
]
_connectors = [
("LPC", {
"GBTCLK0_M2C_P": "F10",
"GBTCLK0_M2C_N": "E10",
"LA01_CC_P": "J20",
"LA01_CC_N": "J21",
"LA05_P": "M21",
"LA05_N": "L21",
"LA09_P": "H20",
"LA09_N": "G20",
"LA13_P": "K17",
"LA13_N": "J17",
"LA17_CC_P": "B17",
"LA17_CC_N": "B18",
"LA23_P": "B21",
"LA23_N": "A21",
"LA26_P": "F18",
"LA26_N": "E18",
"CLK0_M2C_P": "J19",
"CLK0_M2C_N": "A19",
"LA02_P": "M18",
"LA02_N": "L18",
"LA04_P": "N20",
"LA04_N": "M20",
"LA07_P": "M13",
"LA07_N": "L13",
"LA11_P": "L14",
"LA11_N": "L15",
"LA15_P": "L16",
"LA15_N": "K16",
"LA19_P": "A18",
"LA19_N": "A19",
"LA21_P": "E19",
"LA21_N": "D19",
"LA24_P": "B15",
"LA24_N": "B16",
"LA28_P": "C13",
"LA28_N": "B13",
"LA30_P": "A13",
"LA30_N": "A14",
"LA32_P": "A15",
"LA32_N": "A16",
"LA06_P": "N22",
"LA06_N": "M22",
"LA10_P": "K21",
"LA10_N": "K22",
"LA14_P": "J22",
"LA14_N": "H22",
"LA18_CC_P": "D17",
"LA18_CC_N": "C17",
"LA27_P": "B20",
"LA27_N": "A20",
"CLK1_M2C_P": "C18",
"CLK1_M2C_N": "C19",
"LA00_CC_P": "K18",
"LA00_CC_N": "K19",
"LA03_P": "N18",
"LA03_N": "N19",
"LA08_P": "M15",
"LA08_N": "M16",
"LA12_P": "L19",
"LA12_N": "L20",
"LA16_P": "G17",
"LA16_N": "G18",
"LA20_P": "F19",
"LA20_N": "F20",
"LA22_P": "E21",
"LA22_N": "D21",
"LA25_P": "F16",
"LA25_N": "E17",
"LA29_P": "C14",
"LA29_N": "C15",
"LA31_P": "E13",
"LA31_N": "E14",
"LA33_P": "F13",
"LA33_N": "F14",
}
)
]
class Platform(XilinxPlatform):
default_clk_name = "clk100"
default_clk_period = 10.0
def __init__(self, toolchain="vivado", programmer="vivado"):
XilinxPlatform.__init__(self, "xc7a200t-sbg484-1", _io,
XilinxPlatform.__init__(self, "xc7a200t-sbg484-1", _io, _connectors,
toolchain=toolchain)
self.toolchain.bitstream_commands = \
["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]