mirror of
https://github.com/enjoy-digital/litex.git
synced 2025-01-04 09:52:26 -05:00
targets/simple: pass kwargs
This commit is contained in:
parent
b26ac465bd
commit
ac97815619
1 changed files with 2 additions and 2 deletions
|
@ -60,10 +60,10 @@ class _CRG(Module):
|
||||||
class SimpleSoC(SDRAMSoC):
|
class SimpleSoC(SDRAMSoC):
|
||||||
default_platform = "papilio_pro"
|
default_platform = "papilio_pro"
|
||||||
|
|
||||||
def __init__(self, platform):
|
def __init__(self, platform, **kwargs):
|
||||||
clk_freq = 80*1000*1000
|
clk_freq = 80*1000*1000
|
||||||
SDRAMSoC.__init__(self, platform, clk_freq,
|
SDRAMSoC.__init__(self, platform, clk_freq,
|
||||||
cpu_reset_address=0x160000)
|
cpu_reset_address=0x160000, **kwargs)
|
||||||
|
|
||||||
self.submodules.crg = _CRG(platform, clk_freq)
|
self.submodules.crg = _CRG(platform, clk_freq)
|
||||||
|
|
||||||
|
|
Loading…
Reference in a new issue