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Stream2Wishbone: drive sink.ready line

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This commit is contained in:
Michael Betz 2020-10-04 18:19:39 -07:00
parent 6e3e979a0b
commit acdfae202b
1 changed files with 7 additions and 1 deletions
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8
litex/soc/cores/uart.py
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@ -259,7 +259,6 @@ class Stream2Wishbone(Module):
self.sink = sink = stream.Endpoint([("data", 8)]) if phy is None else phy.source self.sink = sink = stream.Endpoint([("data", 8)]) if phy is None else phy.source
self.source = source = stream.Endpoint([("data", 8)]) if phy is None else phy.sink self.source = source = stream.Endpoint([("data", 8)]) if phy is None else phy.sink
self.wishbone = wishbone.Interface() self.wishbone = wishbone.Interface()
self.comb += sink.ready.eq(1) # Always accept incoming stream.
# # # # # #
@ -280,6 +279,7 @@ class Stream2Wishbone(Module):
self.submodules += fsm, timer self.submodules += fsm, timer
self.comb += fsm.reset.eq(timer.done) self.comb += fsm.reset.eq(timer.done)
fsm.act("RECEIVE-CMD", fsm.act("RECEIVE-CMD",
sink.ready.eq(1),
NextValue(bytes_count, 0), NextValue(bytes_count, 0),
NextValue(words_count, 0), NextValue(words_count, 0),
If(sink.valid, If(sink.valid,
@ -288,12 +288,14 @@ class Stream2Wishbone(Module):
) )
) )
fsm.act("RECEIVE-LENGTH", fsm.act("RECEIVE-LENGTH",
sink.ready.eq(1),
If(sink.valid, If(sink.valid,
NextValue(length, sink.data), NextValue(length, sink.data),
NextState("RECEIVE-ADDRESS") NextState("RECEIVE-ADDRESS")
) )
) )
fsm.act("RECEIVE-ADDRESS", fsm.act("RECEIVE-ADDRESS",
sink.ready.eq(1),
If(sink.valid, If(sink.valid,
NextValue(address, Cat(sink.data, address)), NextValue(address, Cat(sink.data, address)),
NextValue(bytes_count, bytes_count + 1), NextValue(bytes_count, bytes_count + 1),
@ -311,6 +313,7 @@ class Stream2Wishbone(Module):
) )
) )
fsm.act("RECEIVE-DATA", fsm.act("RECEIVE-DATA",
sink.ready.eq(1),
If(sink.valid, If(sink.valid,
NextValue(data, Cat(sink.data, data)), NextValue(data, Cat(sink.data, data)),
NextValue(bytes_count, bytes_count + 1), NextValue(bytes_count, bytes_count + 1),
@ -325,6 +328,7 @@ class Stream2Wishbone(Module):
self.wishbone.sel.eq(2**(data_width//8) - 1) self.wishbone.sel.eq(2**(data_width//8) - 1)
] ]
fsm.act("WRITE-DATA", fsm.act("WRITE-DATA",
sink.ready.eq(0),
self.wishbone.stb.eq(1), self.wishbone.stb.eq(1),
self.wishbone.we.eq(1), self.wishbone.we.eq(1),
self.wishbone.cyc.eq(1), self.wishbone.cyc.eq(1),
@ -339,6 +343,7 @@ class Stream2Wishbone(Module):
) )
) )
fsm.act("READ-DATA", fsm.act("READ-DATA",
sink.ready.eq(0),
self.wishbone.stb.eq(1), self.wishbone.stb.eq(1),
self.wishbone.we.eq(0), self.wishbone.we.eq(0),
self.wishbone.cyc.eq(1), self.wishbone.cyc.eq(1),
@ -352,6 +357,7 @@ class Stream2Wishbone(Module):
cases[i] = source.data.eq(data[8*n:]) cases[i] = source.data.eq(data[8*n:])
self.comb += Case(bytes_count, cases) self.comb += Case(bytes_count, cases)
fsm.act("SEND-DATA", fsm.act("SEND-DATA",
sink.ready.eq(0),
source.valid.eq(1), source.valid.eq(1),
If(source.ready, If(source.ready,
NextValue(bytes_count, bytes_count + 1), NextValue(bytes_count, bytes_count + 1),