soc/cores/clock/efinix.py: register_clkin: uses clkin.name_override as input_signal name when name is not provided and PLL is configured in CORE or INTERNAL mode, create_clkout: added PLL name in clk_name str

litex/build/efinix/platform.py

@@ -31,6 +31,7 @@ class EfinixPlatform(GenericPlatform):
         self.iobank_info  = iobank_info
         self.spi_mode     = spi_mode
         self.spi_width    = spi_width
+        self.clks         = {}
         if self.device[:2] == "Ti":
             self.family = "Titanium"
         else:

litex/soc/cores/clock/efinix.py

@@ -89,9 +89,16 @@ class EFINIXPLL(LiteXModule):
             self.logger.info("Clock source: {}, using EXT_CLK{}".format(block["input_clock"], clock_no))
             self.platform.get_pll_resource(pll_res)
         else:
+            if name != "":
+                input_signal = name
+            elif clkin is not None:
+                input_signal = clkin.name_override
+            else:
+                self.logger.error("No clkin name nor clkin provided, can't continue")
+                quit()
             block["input_clock"]  = "INTERNAL" if self.type == "TITANIUMPLL" else "CORE"
             block["resource"]     = self.platform.get_free_pll_resource()
-            block["input_signal"] = name
+            block["input_signal"] = input_signal
             self.logger.info("Clock source: {}".format(block["input_clock"]))
 
         self.logger.info("PLL used     : " + colorer(str(self.platform.pll_used), "cyan"))
@@ -107,7 +114,7 @@ class EFINIXPLL(LiteXModule):
         clk_out_name = f"{self.name}_clkout{self.nclkouts}" if name == "" else name
 
         if cd is not None:
-            clk_name = f"{cd.name}_clk"
+            clk_name = f"{cd.name}_{self.name}_clk"
             clk_out_name = clk_name # To unify constraints names
             self.platform.add_extension([(clk_out_name, 0, Pins(1))])
             clk_out = self.platform.request(clk_out_name)