Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

gen/fhdl/verilog: Add Verilog Timescale generation.

This commit is contained in:
Florent Kermarrec 2022-11-04 08:15:36 +01:00
parent 2ae445018a
commit adea7879d7
1 changed files with 27 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

30
litex/gen/fhdl/verilog.py
View File

@ -74,6 +74,14 @@ def _print_separator(msg=""):
r += "\n" r += "\n"
return r return r
# ------------------------------------------------------------------------------------------------ #
# TIMESCALE #
# ------------------------------------------------------------------------------------------------ #
def _print_timescale(time_unit="1ns", time_precision="1ps"):
r = f"`timescale {time_unit} / {time_precision}\n"
return r
# ------------------------------------------------------------------------------------------------ # # ------------------------------------------------------------------------------------------------ #
# RESERVED KEYWORDS # # RESERVED KEYWORDS #
# ------------------------------------------------------------------------------------------------ # # ------------------------------------------------------------------------------------------------ #
@ -517,9 +525,17 @@ class DummyAttrTranslate(dict):
return (k, "true") return (k, "true")
def convert(f, ios=set(), name="top", platform=None, def convert(f, ios=set(), name="top", platform=None,
special_overrides = dict(), # Verilog parameters.
attr_translate = DummyAttrTranslate(), special_overrides = dict(),
regular_comb = True): attr_translate = DummyAttrTranslate(),
regular_comb = True,
# Sim parameters.
time_unit = "1ns",
time_precision = "1ps",
):
# Build Logic.
# ------------
# Create ConvOutput. # Create ConvOutput.
r = ConvOutput() r = ConvOutput()
@ -584,11 +600,18 @@ def convert(f, ios=set(), name="top", platform=None,
# Build Verilog. # Build Verilog.
# -------------- # --------------
verilog = "" verilog = ""
# Banner.
verilog += _print_banner( verilog += _print_banner(
filename = name, filename = name,
device = getattr(platform, "device", "Unknown") device = getattr(platform, "device", "Unknown")
) )
# Timescale.
verilog += _print_timescale(
time_unit = time_unit,
time_precision = time_precision
)
# Module Definition. # Module Definition.
verilog += _print_separator("Module") verilog += _print_separator("Module")
verilog += _print_module(f, ios, name, ns, attr_translate) verilog += _print_module(f, ios, name, ns, attr_translate)
@ -622,6 +645,7 @@ def convert(f, ios=set(), name="top", platform=None,
# Module End. # Module End.
verilog += "endmodule\n" verilog += "endmodule\n"
# Trailer.
verilog += _print_trailer() verilog += _print_trailer()
r.set_main_source(verilog) r.set_main_source(verilog)