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software/liblitedram: add sdrmpr functions.
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2 changed files with 67 additions and 0 deletions
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@ -841,4 +841,66 @@ int sdrinit(void)
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return 1;
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}
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#define MPR0_SEL (0 << 0)
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#define MPR1_SEL (1 << 0)
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#define MPR2_SEL (2 << 0)
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#define MPR3_SEL (3 << 0)
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#define MPR_ENABLE (1 << 2)
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#define MPR_READ_SERIAL (0 << 11)
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#define MPR_READ_PARALLEL (1 << 11)
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#define MPR_READ_STAGGERED (2 << 11)
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void sdrmrwr(char reg, int value) {
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sdram_dfii_pi0_address_write(value);
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sdram_dfii_pi0_baddress_write(reg);
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command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
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}
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void sdrmpron(char mpr)
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{
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sdrmrwr(3, MPR_READ_SERIAL | MPR_ENABLE | mpr);
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}
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void sdrmproff(void)
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{
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sdrmrwr(3, 0);
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}
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void sdrmpr(void)
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{
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int module, phase;
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printf("Read SDRAM MPR...\n");
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/* rst phy */
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for(module=0; module<SDRAM_PHY_MODULES; module++) {
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#ifdef SDRAM_PHY_WRITE_LEVELING_CAPABLE
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write_delay_rst(module);
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#endif
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read_delay_rst(module);
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read_bitslip_rst(module);
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}
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/* software control */
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sdrsw();
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printf("Reads with MPR0 (0b01010101) enabled...\n");
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sdrmpron(MPR0_SEL);
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command_prd(DFII_COMMAND_CAS|DFII_COMMAND_CS|DFII_COMMAND_RDDATA);
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cdelay(15);
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for (module=0; module < SDRAM_PHY_MODULES; module++) {
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printf("m%d: ", module);
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for(phase=0; phase<SDRAM_PHY_PHASES; phase++) {
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printf("%d", MMPTR(sdram_dfii_pix_rddata_addr[phase]+4*(SDRAM_PHY_MODULES-module-1)) & 0x1);
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printf("%d", MMPTR(sdram_dfii_pix_rddata_addr[phase]+4*(2*SDRAM_PHY_MODULES-module-1)) & 0x1);
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}
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printf("\n");
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}
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sdrmproff();
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/* hardware control */
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sdrhw();
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}
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#endif
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@ -23,4 +23,9 @@ int sdrlevel(void);
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void sdrcal(void);
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int sdrinit(void);
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void sdrmrwr(char reg, int value);
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void sdrmpron(char mpr);
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void sdrmproff(void);
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void sdrmpr(void);
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#endif /* __SDRAM_H */
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