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targets: fix typos in previous changes.

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This commit is contained in:
Florent Kermarrec 2020-03-21 18:26:58 +01:00
parent c547b2cc29
commit ae6ef923af
5 changed files with 8 additions and 8 deletions
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2
litex/boards/targets/kcu105.py
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@ -54,7 +54,7 @@ class BaseSoC(SoCCore):
platform = kcu105.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, with_ethernet=False, **kwargs)
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)

2
litex/boards/targets/netv2.py
View file

@ -49,7 +49,7 @@ class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, **kwargs):
platform = netv2.Platform()
# SoCCore ---------------------------------------------------------------------------------
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------

4
litex/boards/targets/nexys4ddr.py
View file

@ -54,8 +54,8 @@ class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(75e6), with_ethernet=False, **kwargs):
platform = nexys4ddr.Platform()
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# SoCCore ----------------------------------_-----------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)

2
litex/boards/targets/ulx3s.py
View file

@ -10,7 +10,7 @@ import sys
from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from litex_boards.platforms import ulx3s
from litex.boards.platforms import ulx3s
from litex.build.lattice.trellis import trellis_args, trellis_argdict

6
litex/boards/targets/versa_ecp5.py
View file

@ -71,12 +71,12 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCSDRAM):
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(75e6), with_ethernet=False, toolchain="trellis", **kwargs):
platform = versa_ecp5.Platform(toolchain=toolchain)
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# SoCCore -----------------------------------------_----------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)