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10
.travis.yml
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@ -15,12 +15,12 @@ before_install:
- conda install anaconda-client numpydoc
install:
# Install iverilog package.
- "sudo add-apt-repository -y ppa:mithro/iverilog-backport"
- "sudo apt-get update"
- "sudo apt-get install iverilog"
- "iverilog -v; true"
# - "sudo add-apt-repository -y ppa:mithro/iverilog-backport"
# - "sudo apt-get update"
# - "sudo apt-get install iverilog"
# - "iverilog -v; true"
# Build the vpi module.
- "(cd vpi; make; sudo make install)"
# - "(cd vpi; make; sudo make install)"
# Install verilator package
- "sudo apt-get install verilator"
- "verilator --version; true"

4
README.md → README.rst
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@ -47,8 +47,8 @@ http://m-labs.hk/gateware.html
#### Quick intro
```python
from migen.fhdl.std import *
from mibuild.platforms import m1
from migen import *
from migen.build.platforms import m1
plat = m1.Platform()
led = plat.request("user_led")
m = Module()

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conda/migen/meta.yaml
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@ -4,7 +4,7 @@ package:
source:
git_url: https://github.com/m-labs/migen
git_tag: master
git_tag: new
build:
noarch_python: true

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doc/bus.rst
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Bus support
###########
Migen Bus contains classes providing a common structure for master and slave interfaces of the following buses:
* Wishbone [wishbone]_, the general purpose bus recommended by Opencores.
* CSR-2 (see :ref:`csr2`), a low-bandwidth, resource-sensitive bus designed for accessing the configuration and status registers of cores from software.
* LASMIbus (see :ref:`lasmi`), a bus optimized for use with a high-performance frequency-ratio SDRAM controller.
* DFI [dfi]_ (partial), a standard interface protocol between memory controller logic and PHY interfaces.
.. [wishbone] http://cdn.opencores.org/downloads/wbspec_b4.pdf
.. [dfi] http://www.ddr-phy.org/
It also provides interconnect components for these buses, such as arbiters and address decoders. The strength of the Migen procedurally generated logic can be illustrated by the following example: ::
self.submodules.wbcon = wishbone.InterconnectShared(
[cpu.ibus, cpu.dbus, ethernet.dma, audio.dma],
[(lambda a: a[27:] == 0, norflash.bus),
(lambda a: a[27:] == 1, wishbone2lasmi.wishbone),
(lambda a: a[27:] == 3, wishbone2csr.wishbone)])
In this example, the interconnect component generates a 4-way round-robin arbiter, multiplexes the master bus signals into a shared bus, and connects all slave interfaces to the shared bus, inserting the address decoder logic in the bus cycle qualification signals and multiplexing the data return path. It can recognize the signals in each core's bus interface thanks to the common structure mandated by Migen Bus. All this happens automatically, using only that much user code.
Configuration and Status Registers
**********************************
.. _csr2:
CSR-2 bus
=========
The CSR-2 bus is a low-bandwidth, resource-sensitive bus designed for accessing the configuration and status registers of cores from software.
It is the successor of the CSR bus used in Milkymist SoC 1.x, with two modifications:
* Up to 32 slave devices (instead of 16)
* Data words are 8 bits (instead of 32)
.. _bank:
Generating register banks
=========================
Migen Bank is a system comparable to wishbone-gen [wbgen]_, which automates the creation of configuration and status register banks and interrupt/event managers implemented in cores.
.. [wbgen] http://www.ohwr.org/projects/wishbone-gen
Bank takes a description made up of a list of registers and generates logic implementing it with a slave interface compatible with Migen Bus.
The lowest-level description of a register is provided by the ``CSR`` class, which maps to the value at a single address on the target bus. The width of the register needs to be less than or equal to the bus word width. All accesses are atomic. It has the following signal properties to interface to the user design:
* ``r``, which contains the data written from the bus interface.
* ``re``, which is the strobe signal for ``r``. It is active for one cycle, after or during a write from the bus. ``r`` is only valid when ``re`` is high.
* ``w``, which must provide at all times the value to be read from the bus.
Names of CSRs can be omitted if they can be extracted from the variable name. When using this automatic naming feature, prefixes ``_``, ``r_`` and ``_r_`` are removed.
Compound CSRs (which are transformed into ``CSR`` plus additional logic for implementation) provide additional features optimized for common applications.
The ``CSRStatus`` class is meant to be used as a status register that is read-only from the CPU. The user design is expected to drive its ``status`` signal. The advantage of using ``CSRStatus`` instead of using ``CSR`` and driving ``w`` is that the width of ``CSRStatus`` can be arbitrary. Status registers larger than the bus word width are automatically broken down into several ``CSR`` registers to span several addresses. Be careful, though: the atomicity of reads is not guaranteed.
The ``CSRStorage`` class provides a memory location that can be read and written by the CPU, and read and optionally written by the design. It can also span several CSR addresses. An optional mechanism for atomic CPU writes is provided; when enabled, writes to the first CSR addresses go to a back-buffer whose contents are atomically copied to the main buffer when the last address is written. When ``CSRStorage`` can be written to by the design, the atomicity of reads by the CPU is not guaranteed.
A module can provide bus-independent CSRs by implementing a ``get_csrs`` method that returns a list of instances of the classes described above. Similary, bus-independent memories can be returned as a list by a ``get_memories`` method.
To avoid listing those manually, a module can inherit from the ``AutoCSR`` class, which provides ``get_csrs`` and ``get_memories`` methods that scan for CSR and memory attributes and return their list. If the module has child objects that implement ``get_csrs`` or ``get_memories``, they will be called by the ``AutoCSR`` methods and their CSR and memories added to the lists returned, with the child objects' names as prefixes.
Generating interrupt controllers
================================
The event manager provides a systematic way to generate standard interrupt controllers.
Its constructor takes as parameters one or several *event sources*. An event source is an instance of either:
* ``EventSourcePulse``, which contains a signal ``trigger`` that generates an event when high. The event stays asserted after the ``trigger`` signal goes low, and until software acknowledges it. An example use is to pulse ``trigger`` high for 1 cycle after the reception of a character in a UART.
* ``EventSourceProcess``, which contains a signal ``trigger`` that generates an event on its falling edge. The purpose of this event source is to monitor the status of processes and generate an interrupt on their completion. The signal ``trigger`` can be connected to the ``busy`` signal of a dataflow actor, for example.
* ``EventSourceLevel``, whose ``trigger`` contains the instantaneous state of the event. It must be set and released by the user design. For example, a DMA controller with several slots can use this event source to signal that one or more slots require CPU attention.
The ``EventManager`` provides a signal ``irq`` which is driven high whenever there is a pending and unmasked event. It is typically connected to an interrupt line of a CPU.
The ``EventManager`` provides a method ``get_csrs``, that returns a bus-independent list of CSRs to be used with Migen Bank as explained above. Each event source is assigned one bit in each of those registers. They are:
* ``status``: contains the current level of the trigger line of ``EventSourceProcess`` and ``EventSourceLevel`` sources. It is 0 for ``EventSourcePulse``. This register is read-only.
* ``pending``: contains the currently asserted events. Writing 1 to the bit assigned to an event clears it.
* ``enable``: defines which asserted events will cause the ``irq`` line to be asserted. This register is read-write.
.. _lasmi:
Lightweight Advanced System Memory Infrastructure
*************************************************
Rationale
=========
The lagging of the DRAM semiconductor processes behind the logic processes has led the industry into a subtle way of ever increasing memory performance.
Modern devices feature a DRAM core running at a fraction of the logic frequency, whose wide data bus is serialized and deserialized to and from the faster clock domain. Further, the presence of more banks increases page hit rate and provides opportunities for parallel execution of commands to different banks.
A first-generation SDR-133 SDRAM chip runs both DRAM, I/O and logic at 133MHz and features 4 banks. A 16-bit chip has a 16-bit DRAM core.
A newer DDR3-1066 chip still runs the DRAM core at 133MHz, but the logic at 533MHz (4 times the DRAM frequency) and the I/O at 1066Mt/s (8 times the DRAM frequency). A 16-bit chip has a 128-bit internal DRAM core. Such a device features 8 banks. Note that the serialization also introduces multiplied delays (e.g. CAS latency) when measured in number of cycles of the logic clock.
To take full advantage of these new architectures, the memory controller should be able to peek ahead at the incoming requests and service several of them in parallel, while respecting the various timing specifications of each DRAM bank and avoiding conflicts for the shared data lines. Going further in this direction, a controller able to complete transfers out of order can provide even more performance by:
#. grouping requests by DRAM row, in order to minimize time spent on precharging and activating banks.
#. grouping requests by direction (read or write) in order to minimize delays introduced by bus turnaround and write recovery times.
#. being able to complete a request that hits a page earlier than a concurrent one which requires the cycling of another bank.
The first two techniques are explained with more details in [drreorder]_.
.. [drreorder] http://www.xilinx.com/txpatches/pub/documentation/misc/improving%20ddr%20sdram%20efficiency.pdf
Migen and MiSoC implement their own bus, called LASMIbus, that features the last two techniques. Grouping by row had been previously explored with ASMI, but difficulties in achieving timing closure at reasonable latencies in FPGA combined with uncertain performance pay-off for some applications discouraged work in that direction.
Topology and transactions
=========================
The LASMI consists of one or several memory controllers (e.g. LASMIcon from MiSoC), multiple masters, and crossbar interconnect.
Each memory controller can expose several bank machines to the crossbar. This way, requests to different SDRAM banks can be processed in parallel.
Transactions on LASMI work as follows:
1. The master presents a valid address and write enable signals, and asserts its strobe signal.
2. The crossbar decodes the bank address and, in a multi-controller configuration, the controller address and connects the master to the appropriate bank machine.
3. The bank machine acknowledges the request from the master. The master can immediately issue a new request to the same bank machine, without waiting for data.
4. The bank machine sends data acknowledgements to the master, in the same order as it issued requests. After receiving a data acknowldegement, the master must either:
* present valid data after a fixed number of cycles (for writes). Masters must hold their data lines at 0 at all other times so that they can be simply ORed for each controller to produce the final SDRAM write data.
* sample the data bus after a fixed number of cycles (for reads).
5. In a multi-controller configuration, the crossbar multiplexes write and data signals to route data to and from the appropriate controller.
When there are queued requests (i.e. more request acknowledgements than data acknowledgements), the bank machine asserts its ``lock`` signal which freezes the crossbar connection between the master and the bank machine. This simplifies two problems:
#. Determining to which master a data acknowledgement from a bank machine should be sent.
#. Having to deal with a master queuing requests into multiple different bank machines which may collectively complete them in a different order than the master issued them.
For each master, transactions are completed in-order by the memory system. Reordering may only occur between masters, e.g. a master issuing a request that hits a page may have it completed sooner than a master requesting earlier a precharge/activate cycle of another bank.
It is suggested that memory controllers use an interface to a PHY compatible with DFI [dfi]_. The DFI clock can be the same as the LASMIbus clock, with optional serialization and deserialization taking place across the PHY, as specified in the DFI standard.
SDRAM burst length and clock ratios
===================================
A system using LASMI must set the SDRAM burst length B, the LASMIbus word width W and the ratio between the LASMIbus clock frequency Fa and the SDRAM I/O frequency Fi so that all data transfers last for exactly one LASMIbus cycle.
More explicitly, these relations must be verified:
B = Fi/Fa
W = B*[number of SDRAM I/O pins]
For DDR memories, the I/O frequency is twice the logic frequency.

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Case studies
############
A VGA framebuffer core
**********************
Purpose
=======
The purpose of the VGA framebuffer core is to scan a buffer in system memory and generate an appropriately timed video signal in order to display the picture from said buffer on a regular VGA monitor.
The core is meant to be integrated in a SoC and is controllable by a CPU which can set parameters such as the framebuffer address, video resolution and timing parameters.
This case study highlights what tools Migen provides to design such a core.
Architecture
============
The framebuffer core is designed using the Migen dataflow system (see :ref:`dataflow`). Its block diagram is given in the figure below:
.. figure:: fbflow.png
:scale: 50 %
Data flow graph of the framebuffer core.
Actors drawn with a blue background are designed specifically for the framebuffer cores, the others are generic actors from the Migen library. Migen also provides the interconnect logic between the actors.
Frame initiator
===============
The frame initiator generates tokens that correspond each to one complete scan of the picture (active video, synchronization pulses, front and back porches). The token contains the address and the length of the framebuffer used for the active video region, and timing parameters to generate the synchronization and porches.
Switching the framebuffer address (without tearing) is simply done by generating a token with the new address. Tearing will not occur since the new token will accepted only after the one from the previous frame has been processed (i.e. all addresses within the previous frame have been generated).
Video resolution can be changed in a similar way.
To interface with the CPU, the frame initiator uses Migen to provide a CSR bank (see :ref:`bank`).
Pixel fetcher
=============
The pixel fetcher is made up of the address generator, the LASMI reader and the unpacker.
The address generator is a simple counter that takes one token containing the pair ``(base, length)`` and generates ``length`` tokens containing ``base``, ..., ``base+length-1``. It is implemented using a Migen library component (see :ref:`intsequence`).
Those addresses are fed into the LASMI reader (see :ref:`busactors`) that fetches the corresponding locations from the system memory. The LASMI reader design supports several outstanding requests, which enables it to sustain a high throughput in spite of memory latency. This feature makes it possible to utilize the available memory bandwidth to the full extent, and reduces the need for on-chip buffering.
LASMI memory words are wide and contain several pixels. The unpacking actor (see :ref:`structuring`) takes a token containing a memory word and "chops" it into multiple tokens containing one pixel each.
Video timing generator
======================
The video timing generator is the central piece of the framebuffer core. It takes one token containing the timing parameters of a frame, followed by as many tokens as there are pixels in the frame. It generates tokens containing the status of the horizontal/vertical synchronization signals and red/green/blue values. When the contents of those tokens are sent out at the pixel clock rate (and the red/green/blue value converted to analog), they form a valid video signal for one frame.
DAC driver
==========
The DAC driver accepts and buffers the output tokens from the video timing generator, and sends their content to the DAC and video port at the pixel clock rate using an asynchronous FIFO.

12
doc/conf.py
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@ -11,8 +11,6 @@
# All configuration values have a default; values that are commented out
# serve to show the default.
import sys, os
# If extensions (or modules to document with autodoc) are in another directory,
# add these directories to sys.path here. If the directory is relative to the
# documentation root, use os.path.abspath to make it absolute, like shown here.
@ -47,16 +45,16 @@ master_doc = 'index'
# General information about the project.
project = u'Migen'
copyright = u'2012, Sebastien Bourdeauducq'
copyright = u'2011-2015, M-Labs Limited'
# The version info for the project you're documenting, acts as replacement for
# |version| and |release|, also used in various other places throughout the
# built documents.
#
# The short X.Y version.
version = 'X'
version = '1.0'
# The full version, including alpha/beta/rc tags.
release = 'X'
release = '1.0'
# The language for content autogenerated by Sphinx. Refer to documentation
# for a list of supported languages.
@ -90,7 +88,7 @@ exclude_patterns = ['_build']
pygments_style = 'sphinx'
# A list of ignored prefixes for module index sorting.
modindex_common_prefix = ['migen.', 'mibuild.']
modindex_common_prefix = ['migen.']
numpydoc_show_class_members = False
@ -98,7 +96,7 @@ numpydoc_show_class_members = False
# The theme to use for HTML and HTML Help pages. See the documentation for
# a list of builtin themes.
html_theme = 'default'
html_theme = 'alabaster'
# Theme options are theme-specific and customize the look and feel of a theme
# further. For a list of options available for each theme, see the

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.. _dataflow:
Dataflow
########
Many hardware acceleration problems can be expressed in the dataflow paradigm. It models a program as a directed graph of the data flowing between functions. The nodes of the graph are functional units called actors, and the edges represent the connections (transporting data) between them.
Actors communicate by exchanging data units called tokens. A token contains arbitrary (user-defined) data, which is a record containing one or many fields, a field being a bit vector or another record. Token exchanges are atomic (i.e. all fields are transferred at once from the transmitting actor to the receiving actor).
Actors
******
Actors and endpoints
====================
Actors in Migen are implemented in FHDL. This low-level approach maximizes the practical flexibility: for example, an actor can manipulate the bus signals to implement a DMA master in order to read data from system memory (see :ref:`busactors`).
Token exchange ports of actors are called endpoints. Endpoints are unidirectional and can be sources (which transmit tokens out of the actor) or sinks (which receive tokens into the actor).
.. figure:: actors_endpoints.png
:scale: 50 %
Actors and endpoints.
The flow of tokens is controlled using two handshake signals (strobe and acknowledgement) which are implemented by every endpoint. The strobe signal is driven by sources, and the acknowledgement signal by sinks.
======= ======= ====================================================================================================
``stb`` ``ack`` Situation
======= ======= ====================================================================================================
0 0 The source endpoint does not have data to send, and the sink endpoint is not ready to
accept data.
0 1 The sink endpoint is ready to accept data, but the source endpoint has currently no data
to send. The sink endpoint is not required to keep its ``ack`` signal asserted.
1 0 The source endpoint is trying to send data to the sink endpoint, which is currently not
ready to accept it. The transaction is *stalled*. The source endpoint must keep ``stb``
asserted and continue to present valid data until the transaction is completed.
1 1 The source endpoint is sending data to the sink endpoint which is ready to accept it. The
transaction is *completed*. The sink endpoint must register the incoming data, as the
source endpoint is not required to hold it valid at the next cycle.
======= ======= ====================================================================================================
It is permitted to generate an ``ack`` signal combinatorially from one or several ``stb`` signals. However, there should not be any combinatorial path from an ``ack`` to a ``stb`` signal.
Actors are FHDL modules that have one or several endpoint attributes of the ``migen.flow.actor.Sink`` or ``migen.flow.actor.Source`` type, and a ``busy`` signal.
Endpoint constructors take as parameter the layout of the data record that the endpoint is dealing with.
Record layouts are a list of fields. Each field is described by a pair consisting of:
* The field's name.
* Either a bit width or a (bit width, signedness) pair if the field is a bit vector, or another record layout if the field is a lower-level record.
For example, this code: ::
class MyActor(Module):
def __init__(self):
self.busy = Signal()
self.operands = Sink([("a", 16), ("b", 16)])
self.result = Source([("r", 17)])
creates an actor with:
* One sink named ``operands`` accepting data structured as a 16-bit field ``a`` and a 16-bit field ``b``. Note that this is functionally different from having two endpoints ``a`` and ``b``, each accepting a single 16-bit field. With a single endpoint, the data is strobed when *both* ``a`` and ``b`` are valid, and ``a`` and ``b`` are *both* acknowledged *atomically*. With two endpoints, the actor has to deal with accepting ``a`` and ``b`` independently. Plumbing actors (see :ref:`plumbing`) and abstract networks (see :ref:`actornetworks`) provide a systematic way of converting between these two behaviours, so user actors should implement the behaviour that results in the simplest or highest performance design.
* One source named ``result`` transmitting a single 17-bit field named ``r``.
Accessing the endpoints is done by manipulating the signals inside the ``Source`` and ``Sink`` objects. They hold:
* A signal object ``stb``.
* A signal object ``ack``.
* The data payload ``payload``, which is a record with the layout given to the endpoint constructor.
Endpoints can also be used to manipulate packets, this is done by setting packetized parameter to True which adds:
* A signal object ``sop`` (Start Of Packet).
* A signal object ``eop`` (End Of Packet).
When used in packetized mode, packet parameters (signals that do no change for the duration of a packet) should to be declared in
param_layout. Declaring these signals in payload_layout will works in most cases but will prevent logic optimizations.
Busy signal
===========
The basic actor class creates a ``busy`` control signal that actor implementations should drive.
This signal represents whether the actor's state holds information that will cause the completion of the transmission of output tokens. For example:
* A "buffer" actor that simply registers and forwards incoming tokens should drive 1 on ``busy`` when its register contains valid data pending acknowledgement by the receiving actor, and 0 otherwise.
* An actor sequenced by a finite state machine should drive ``busy`` to 1 whenever the state machine leaves its idle state.
* An actor made of combinatorial logic is stateless and should tie ``busy`` to 0.
.. _schedmod:
Common scheduling models
========================
For the simplest and most common scheduling cases, Migen provides logic to generate the handshake signals and the busy signal. This is done through abstract actor classes that examine the endpoints defined by the user and add logic to drive their control signals (i.e. everything except the payload). The ``__init__`` method of the abstract scheduling class must be called after the user has created the endpoints. The ``busy`` signal is created by the abstract scheduling class.
These classes are usable only when the actor has exactly one sink and one source (but those endpoints can contain an arbitrary data structure), and in the cases listed below.
Combinatorial
-------------
The actor datapath is made entirely of combinatorial logic. The handshake signals pass through. A small integer adder would use this model.
This model is implemented by the ``migen.flow.actor.CombinatorialActor`` class. There are no parameters or additional control signals.
N-sequential
------------
The actor consumes one token at its input, and it produces one output token after N cycles. It cannot accept new input tokens until it has produced its output. A multicycle integer divider would use this model.
This model is implemented by the ``migen.flow.actor.SequentialActor`` class. The constructor of this class takes as parameter the number of cycles N. The class provides an extra control signal ``trigger`` that pulses to 1 for one cycle when the actor should register the inputs and start its processing. The actor is then expected to provide an output after the N cycles and hold it constant until the next trigger pulse.
N-pipelined
-----------
This is similar to the sequential model, but the actor can always accept new input tokens. It produces an output token N cycles of latency after accepting an input token. A pipelined multiplier would use this model.
This model is implemented by the ``migen.flow.actor.PipelinedActor`` class. The constructor takes the number of pipeline stages N. There is an extra control signal ``pipe_ce`` that should enable or disable all synchronous statements in the datapath (i.e. it is the common clock enable signal for all the registers forming the pipeline stages).
The Migen actor library
***********************
.. _plumbing:
Plumbing actors
===============
Plumbing actors arbitrate the flow of data between actors. For example, when a source feeds two sinks, they ensure that each sink receives exactly one copy of each token transmitted by the source.
Most of the time, you will not need to instantiate plumbing actors directly, as abstract actor networks (see :ref:`actornetworks`) provide a more powerful solution and let Migen insert plumbing actors behind the scenes.
Buffer
------
The ``Buffer`` registers the incoming token and retransmits it. It is a pipelined actor with one stage. It can be used to relieve some performance problems or ease timing closure when many levels of combinatorial logic are accumulated in the datapath of a system.
When used in a network, abstract instances of ``Buffer`` are automatically configured by Migen (i.e. the appropriate token layout is set).
Combinator
----------
This actor combines tokens from several sinks into one source.
For example, when the operands of a pipelined multiplier are available independently, the ``Combinator`` can turn them into a structured token that is sent atomically into the multiplier when both operands are available, simplifying the design of the multiplier actor.
Splitter
--------
This actor does the opposite job of the ``Combinator``. It receives a token from its sink, duplicates it into an arbitrary number of copies, and transmits one through each of its sources. It can optionally omit certain fields of the token (i.e. take a subrecord).
For example, an Euclidean division actor generating the quotient and the remainder in one step can transmit both using one token. The ``Splitter`` can then forward the quotient and the remainder independently, as integers, to other actors.
.. _structuring:
Structuring actors
==================
Cast
----
This actor concatenates all the bits from the data of its sink (in the order as they appear in the layout) and connects them to the raw bits of its source (obtained in the same way). The source and the sink layouts must contain the same number of raw bits. This actor is a simple "connect-through" which does not use any hardware resources.
It can be used in conjunction with the bus master actors (see :ref:`busactors`) to destructure (resp. structure) data going to (resp. coming from) the bus.
Unpack
------
This actor takes a token with the fields ``chunk0`` ... ``chunk[N-1]`` (each having the same layout L) and generates N tokens with the layout L containing the data of ``chunk0`` ... ``chunk[N-1]`` respectively.
Pack
----
This actor receives N tokens with a layout L and generates one token with the fields ``chunk0`` ... ``chunk[N-1]`` (each having the same layout L) containing the data of the N incoming tokens respectively.
Simulation actors
=================
When hardware implementation is not desired, Migen lets you program actor behaviour in "regular" Python.
For this purpose, it provides a ``migen.actorlib.sim.SimActor`` class. The constructor takes a generator as parameter, which implements the actor's behaviour. The user must derive the ``SimActor`` class and add endpoint attributes. The ``busy`` signal is provided by the ``SimActor`` class.
Generators can yield ``None`` (in which case, the actor does no transfer for one cycle) or one or a tuple of instances of the ``Token`` class. Tokens for sink endpoints are pulled and the "value" field filled in. Tokens for source endpoints are pushed according to their "value" field. The generator is run again after all transactions are completed.
The possibility to push several tokens at once is important to interact with actors that only accept a group of tokens when all of them are available.
The ``Token`` class contains the following items:
* The name of the endpoint from which it is to be received, or to which it is to be transmitted. This value is not modified by the transaction.
* A dictionary of values corresponding to the fields of the token. Fields that are lower-level records are represented by another dictionary. This item should be set to ``None`` (default) when receiving from a sink.
See ``dataflow.py`` in the examples folder of the Migen sources for a demonstration of the use of these actors.
.. _busactors:
Bus actors
==========
Migen provides a collection of bus-mastering actors, which makes it possible for dataflow systems to access system memory easily and efficiently.
Wishbone reader
---------------
The ``migen.actorlib.dma_wishbone.Reader`` takes a token representing a 30-bit Wishbone address (expressed in words), reads one 32-bit word on the bus at that address, and transmits the data.
It does so using Wishbone classic cycles (there is no burst or cache support). The actor is pipelined and its throughput is only limited by the Wishbone stall cycles.
Wishbone writer
---------------
The ``migen.actorlib.dma_wishbone.Writer`` takes a token containing a 30-bit Wishbone address (expressed in words) and a 32-bit word of data, and writes that word to the bus.
Only Wishbone classic cycles are supported. The throughput is limited by the Wishbone stall cycles only.
LASMI reader
------------
The ``migen.actorlib.dma_lasmi.Reader`` requires a LASMI master port at instantiation time. This port defines the address and data widths of the actor and how many outstanding transactions are supported.
Input tokens contain the raw LASMI address, and output tokens are wide LASMI data words.
LASMI writer
------------
Similarly, Migen provides a LASMI writer actor that accepts tokens containing an address and write data (in the same format as a LASMI word).
Miscellaneous actors
====================
.. _intsequence:
Integer sequence generator
--------------------------
The integer sequence generator either:
* takes a token containing a maximum value N and generates N tokens containing the numbers 0 to N-1.
* takes a token containing a number of values N and a offset O and generates N-O tokens containing the numbers O to O+N-1.
The actor instantiation takes several parameters:
* the number of bits needed to represent the maximum number of generated values.
* the number of bits needed to represent the maximum offset. When this value is 0 (default), then offsets are not supported and the sequence generator accepts tokens which contain the maximum value alone.
The integer sequence generator can be used in combination with bus actors to generate addresses and read contiguous blocks of system memory (see :ref:`busactors`).
.. _actornetworks:
Actor networks
**************
Graph definition
================
Migen represents an actor network using the ``migen.flow.network.DataFlowGraph`` class (a directed graph with self-loops and parallel edges).
Nodes of the graph are either:
* An existing actor (*physical actor*).
* An instance of ``migen.flow.network.AbstractActor``, containing the actor class and a dictionary (*abstract actor*). It means that the actor class should be instantiated with the parameters from the dictionary. This form is needed to enable optimizations such as actor duplication or sharing during elaboration.
Edges of the graph represent the flow of data between actors. They have the following data properties:
* ``source``: a string containing the name of the source endpoint, which can be ``None`` (Python's ``None``, not the string ``"None"``) if the transmitting actor has only one source endpoint.
* ``sink``: a string containing the name of the sink endpoint, which can be ``None`` if the transmitting actor has only one sink endpoint.
* ``source_subr``: if only certain fields (a subrecord) of the source endpoint should be included in the connection, their names are listed in this parameter. The ``None`` value connects all fields.
* ``sink_subr``: if the connection should only drive certain fields (a subrecord) of the sink endpoint, they are listed here. The ``None`` value connects all fields.
Migen's ``DataFlowGraph`` class implements a method that makes it easy to add actor connections to a graph: ::
add_connection(source_node, sink_node,
source_ep=None, sink_ep=None, # default: assume nodes have 1 source/sink
# and use that one
source_subr=None, sink_subr=None) # default: use whole record
Abstract and physical networks
==============================
A network (or graph) is abstract if it cannot be physically implemented by only connecting existing records together. More explicitly, a graph is abstract if any of these conditions is met:
#. A node is an abstract actor.
#. A subrecord is used at a source or a sink.
#. A single source feeds more than one sink.
The ``DataFlowGraph`` class implements a method ``is_abstract`` that tests and returns if the network is abstract.
An abstract graph can be turned into a physical graph through *elaboration*.
Elaboration
===========
The most straightforward elaboration process goes as follows:
#. Whenever several sources drive different fields of a single sink, insert a ``Combinator`` plumbing actor. A ``Combinator`` should also be inserted when a single source drive only certain fields of a sink.
#. Whenever several sinks are driven by a single source (possibly by different fields of that source), insert a ``Splitter`` plumbing actor. A ``Splitter`` should also be inserted when only certain fields of a source drive a sink.
#. Whenever an actor is abstract, instantiate it.
This method is implemented by default by the ``elaborate`` method of the ``DataFlowGraph`` class, that modifies the graph in-place.
Thanks to abstract actors, there are optimization possibilities during this stage:
* Time-sharing an actor to reduce resource utilization.
* Duplicating an actor to increase performance.
* Promoting an actor to a wider datapath to enable time-sharing with another. For example, if a network contains a 16-bit and a 32-bit multiplier, the 16-bit multiplier can be promoted to 32-bit and time-shared.
* Algebraic optimizations.
* Removing redundant actors whose output is only used partially. For example, two instances of divider using the restoring method can be present in a network, and each could generate either the quotient or the remainder of the same integers. Since the restoring method produces both results at the same time, only one actor should be used instead.
None of these optimizations are implemented yet.
Implementation
==============
A physical graph can be implemented and turned into a synthesizable or simulable fragment using the ``migen.flow.network.CompositeActor`` actor.
Performance tools
*****************
The module ``migen.flow.perftools`` provides utilities to analyze the performance of a dataflow network.
The class ``EndpointReporter`` is a simulation object that attaches to an endpoint and measures three parameters:
* The total number of clock cycles per token (CPT). This gives a measure of the raw inverse token rate through the endpoint. The smaller this number, the faster the endpoint operates. Since an endpoint has only one set of synchronous control signals, the CPT value is always superior or equal to 1 (multiple data records can however be packed into a single token, see for example :ref:`structuring`).
* The average number of inactivity cycles per token (IPT). An inactivity cycle is defined as a cycle with the ``stb`` signal deasserted. This gives a measure of the delay between attempts at token transmissions ("slack") on the endpoint.
* The average number of stall cycles per token (NPT). A stall cycle is defined as a cycle with ``stb`` asserted and ``ack`` deasserted. This gives a measure of the "backpressure" on the endpoint, which represents the average number of wait cycles it takes for the source to have a token accepted by the sink. If all tokens are accepted immediately in one cycle, then NPT=0.
In the case of an actor network, the ``DFGReporter`` simulation object attaches an ``EndpointReporter`` to the source endpoint of each edge in the graph. The graph must not be abstract.
The ``DFGReporter`` contains a dictionary ``nodepair_to_ep`` that is keyed by ``(source actor, destination actor)`` pairs. Entries are other dictionaries that are keyed with the name of the source endpoint and return the associated ``EndpointReporter`` objects.
``DFGReporter`` also provides a method ``get_edge_labels`` that can be used in conjunction with NetworkX's [networkx]_ ``draw_networkx_edge_labels`` function to draw the performance report on a graphical representation of the graph (for an example, see :ref:`get_edge_labels`).
.. [networkx] http://networkx.lanl.gov/
.. _get_edge_labels:
.. figure:: get_edge_labels.png
:scale: 55 %
Actor network with performance data from a simulation run.
High-level actor description
****************************
Actors can be written in a subset of Python and automatically compiled into FHDL by using the Pytholite component. This functionality is still very limited for now.

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The FHDL layer
##############
The FHDL domain-specific language
#################################
The Fragmented Hardware Description Language (FHDL) is the lowest layer of Migen. It consists of a formal system to describe signals, and combinatorial and synchronous statements operating on them. The formal system itself is low level and close to the synthesizable subset of Verilog, and we then rely on Python algorithms to build complex structures by combining FHDL elements.
The Fragmented Hardware Description Language (FHDL) is the basis of Migen. It consists of a formal system to describe signals, and combinatorial and synchronous statements operating on them. The formal system itself is low level and close to the synthesizable subset of Verilog, and we then rely on Python algorithms to build complex structures by combining FHDL elements.
The FHDL module also contains a back-end to produce synthesizable Verilog, and some structure analysis and manipulation functionality.
FHDL differs from MyHDL [myhdl]_ in fundamental ways. MyHDL follows the event-driven paradigm of traditional HDLs (see :ref:`background`) while FHDL separates the code into combinatorial statements, synchronous statements, and reset values. In MyHDL, the logic is described directly in the Python AST. The converter to Verilog or VHDL then examines the Python AST and recognizes a subset of Python that it translates into V*HDL statements. This seriously impedes the capability of MyHDL to generate logic procedurally. With FHDL, you manipulate a custom AST from Python, and you can more easily design algorithms that operate on it.
.. [myhdl] http://www.myhdl.org
FHDL is made of several elements, which are briefly explained below. They all can be imported from the ``migen.fhdl.std`` module.
FHDL is made of several elements, which are briefly explained below. They all can be imported directly from the ``migen`` module.
Expressions
***********
Integers and booleans
=====================
Constants
=========
Python integers and booleans can appear in FHDL expressions to represent constant values in a circuit. ``True`` and ``False`` are interpreted as 1 and 0, respectively.
The ``Constant`` object represents a constant, HDL-literal integer. It behaves like specifying integers and booleans but also supports slicing and can have a bit width or signedness different from what is implied by the value it represents.
``True`` and ``False`` are interpreted as 1 and 0, respectively.
Negative integers are explicitly supported. As with MyHDL [countin]_, arithmetic operations return the natural results.
To lighten the syntax, assignments and operators automatically wrap Python integers and booleans into ``Constant``. Additionally, ``Constant`` is aliased to ``C``. The following are valid Migen statements: ``a.eq(0)``, ``a.eq(a + 1)``, ``a.eq(C(42)[0:1])``.
.. [countin] http://www.jandecaluwe.com/hdldesign/counting.html
Signal
======
The signal object represents a value that is expected to change in the circuit. It does exactly what Verilog's "wire" and "reg" and VHDL's "signal" do.
The main point of the signal object is that it is identified by its Python ID (as returned by the :py:func:`id` function), and nothing else. It is the responsibility of the V*HDL back-end to establish an injective mapping between Python IDs and the V*HDL namespace. It should perform name mangling to ensure this. The consequence of this is that signal objects can safely become members of arbitrary Python classes, or be passed as parameters to functions or methods that generate logic involving them.
@ -45,6 +50,7 @@ In case of conflicts, Migen tries first to resolve the situation by prefixing th
Operators
=========
Operators are represented by the ``_Operator`` object, which generally should not be used directly. Instead, most FHDL objects overload the usual Python logic and arithmetic operators, which allows a much lighter syntax to be used. For example, the expression: ::
a * b + c
@ -55,15 +61,18 @@ is equivalent to::
Slices
======
Likewise, slices are represented by the ``_Slice`` object, which often should not be used in favor of the Python slice operation [x:y]. Implicit indices using the forms [x], [x:] and [:y] are supported. Beware! Slices work like Python slices, not like VHDL or Verilog slices. The first bound is the index of the LSB and is inclusive. The second bound is the index of MSB and is exclusive. In V*HDL, bounds are MSB:LSB and both are inclusive.
Concatenations
==============
Concatenations are done using the ``Cat`` object. To make the syntax lighter, its constructor takes a variable number of arguments, which are the signals to be concatenated together (you can use the Python "*" operator to pass a list instead).
To be consistent with slices, the first signal is connected to the bits with the lowest indices in the result. This is the opposite of the way the "{}" construct works in Verilog.
Replications
============
The ``Replicate`` object represents the equivalent of {count{expression}} in Verilog.
Statements
@ -71,6 +80,7 @@ Statements
Assignment
==========
Assignments are represented with the ``_Assign`` object. Since using it directly would result in a cluttered syntax, the preferred technique for assignments is to use the ``eq()`` method provided by objects that can have a value assigned to them. They are signals, and their combinations with the slice and concatenation operators.
As an example, the statement: ::
@ -82,6 +92,7 @@ is equivalent to: ::
If
==
The ``If`` object takes a first parameter which must be an expression (combination of the ``Constant``, ``Signal``, ``_Operator``, ``_Slice``, etc. objects) representing the condition, then a variable number of parameters representing the statements (``_Assign``, ``If``, ``Case``, etc. objects) to be executed when the condition is verified.
The ``If`` object defines a ``Else()`` method, which when called defines the statements to be executed when the condition is not true. Those statements are passed as parameters to the variadic method.
@ -105,10 +116,12 @@ Example: ::
Case
====
The ``Case`` object constructor takes as first parameter the expression to be tested, and a dictionary whose keys are the values to be matched, and values the statements to be executed in the case of a match. The special value ``"default"`` can be used as match value, which means the statements should be executed whenever there is no other match.
Arrays
======
The ``Array`` object represents lists of other objects that can be indexed by FHDL expressions. It is explicitly possible to:
* nest ``Array`` objects to create multidimensional tables.
@ -134,6 +147,7 @@ Specials
Tri-state I/O
=============
A triplet (O, OE, I) of one-way signals defining a tri-state I/O port is represented by the ``TSTriple`` object. Such objects are only containers for signals that are intended to be later connected to a tri-state I/O buffer, and cannot be used as module specials. Such objects, however, should be kept in the design as long as possible as they allow the individual one-way signals to be manipulated in a non-ambiguous way.
The object that can be used in as a module special is ``Tristate``, and it behaves exactly like an instance of a tri-state I/O buffer that would be defined as follows: ::
@ -153,6 +167,7 @@ By default, Migen emits technology-independent behavioral code for a tri-state b
Instances
=========
Instance objects represent the parametrized instantiation of a V*HDL module, and the connection of its ports to FHDL signals. They are useful in a number of cases:
* Reusing legacy or third-party V*HDL code.
@ -170,6 +185,7 @@ These parameters can be:
Memories
========
Memories (on-chip SRAM) are supported using a mechanism similar to instances.
A memory object has the following parameters:
@ -258,7 +274,7 @@ Clock domains are then added to a module using the ``clock_domains`` special att
Summary of special attributes
=============================
.. table:: Summary of special attributes
.. table::
+--------------------------------------------+--------------------------------------------------------------+
| Syntax | Action |
@ -338,16 +354,9 @@ Finalization is automatically invoked at V*HDL conversion and at simulation. It
The clock domain management mechanism explained above happens during finalization.
Simulation
==========
The ``do_simulation`` method of the ``Module`` class can be defined and will be executed at each clock cycle, or the generator-style API can be used by defining ``gen_simulation`` instead. The generator yields the number of cycles it wants to wait for. See :ref:`simulating` for more information on using the simulator.
Simulation of designs with several clock domains is not supported yet.
Conversion for synthesis
************************
Any FHDL module (except, of course, its simulation functions) can be converted into synthesizable Verilog HDL. This is accomplished by using the ``convert`` function in the ``verilog`` module.
Any FHDL module can be converted into synthesizable Verilog HDL. This is accomplished by using the ``convert`` function in the ``verilog`` module.
The Mibuild component provides scripts to interface third-party FPGA tools to Migen and a database of boards for the easy deployment of designs.
The ``migen.build`` component provides scripts to interface third-party FPGA tools (from Xilinx, Altera and Lattice) to Migen, and a database of boards for the easy deployment of designs.

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introduction
fhdl
bus
dataflow
simulation
casestudies
api
synthesis
reference

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Background
**********
Even though the Milkymist system-on-chip [mm]_ is technically successful, it suffers from several limitations stemming from its implementation in manually written Verilog HDL:
Even though the Milkymist system-on-chip [mm]_ had many successes, it suffers from several limitations stemming from its implementation in manually written Verilog HDL:
.. [mm] http://m-labs.hk
@ -38,20 +38,24 @@ Even though the Milkymist system-on-chip [mm]_ is technically successful, it suf
#. Building a memory infrastructure (including bus interconnect, bridges and caches) that can automatically adapt itself at compile-time to any word size of the SDRAM is clumsy and tedious.
#. Building register banks for control, status and interrupt management of cores can also largely benefit from automation.
#. Many hardware acceleration problems can fit into the dataflow programming model. Manual dataflow implementation in V*HDL has, again, a lot of redundancy and potential for human errors. See the Milkymist texture mapping unit [mthesis]_ [mxcell]_ for an example of this. The amount of detail to deal with manually also makes the design space exploration difficult, and therefore hinders the design of efficient architectures.
#. Pre-computation of values, such as filter coefficients for DSP or even simply trigonometric tables, must often be done using external tools whose results are copy-and-pasted (in the best cases, automatically) into the V*HDL source.
#. Pre-computation of values, such as filter coefficients for DSP or even simply trigonometric tables, must often be done using external tools whose results are copy-and-pasted (in the best case, automatically) into the V*HDL source.
.. [mthesis] http://m-labs.hk/thesis/thesis.pdf
.. [mxcell] http://www.xilinx.com/publications/archives/xcell/Xcell77.pdf p30-35
Enter Migen, a Python toolbox for building complex digital hardware. We could have designed a brand new programming language, but that would have been reinventing the wheel instead of being able to benefit from Python's rich features and immense library. The price to pay is a slightly cluttered syntax at times when writing descriptions in FHDL, but we believe this is totally acceptable, particularly when compared to VHDL ;-)
Migen is made up of several related components, which are described in this manual.
Migen is made up of several related components:
#. the base language, FHDL
#. a library of small generic cores
#. a simulator
#. a build system
Installing Migen
****************
Either run the ``setup.py`` installation script or simply set ``PYTHONPATH`` to the root of the source directory.
For simulation support, an extra step is needed. See :ref:`vpisetup`.
Either run the ``setup.py`` installation script or simply set ``PYTHONPATH`` to the root of the source directory.
If you wish to contribute patches, the suggest way to install is;
#. Clone from the git repository at http://github.com/m-labs/migen
@ -61,9 +65,9 @@ If you wish to contribute patches, the suggest way to install is;
Alternative install methods
===========================
* Migen is available for linux-64 and linux-32 through Binstar's conda tool. Instructions are at https://binstar.org/fallen/migen
* Migen can be referenced in a requirements.txt file (used for ``pip install -r requirements.txt``) via ``-e git+http://github.com/m-labs/migen.git#egg=migen``. See the `pip documentation <https://pip.pypa.io/en/latest/reference/pip_install.html#id19>`_ for more information.
* Migen is available for the Anaconda Python distribution. The package can be found at at https://anaconda.org/m-labs/migen
* Migen can be referenced in a requirements.txt file (used for ``pip install -r requirements.txt``) via ``-e git+http://github.com/m-labs/migen.git#egg=migen``. See the pip documentation for more information.
Feedback
********
Feedback concerning Migen or this manual should be sent to the M-Labs developers' mailing list at devel@lists.m-labs.hk.
Feedback concerning Migen or this manual should be sent to the M-Labs developers' mailing list ``devel`` on lists.m-labs.hk.

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migen API Documentation
=======================
API reference
=============
:mod:`fhdl.structure` Module
:mod:`fhdl.structure` module
----------------------------
.. automodule:: migen.fhdl.structure
:members:
:show-inheritance:
:mod:`fhdl.bitcontainer` Module
:mod:`fhdl.bitcontainer` module
-------------------------------
.. automodule:: migen.fhdl.bitcontainer
:members:
:show-inheritance:
:mod:`genlib.fifo` Module
:mod:`genlib.fifo` module
-------------------------
.. automodule:: migen.genlib.fifo
:members:
:show-inheritance:
:mod:`genlib.coding` Module
:mod:`genlib.coding` module
---------------------------
.. automodule:: migen.genlib.coding
:members:
:show-inheritance:
:mod:`genlib.sort` Module
:mod:`genlib.sort` module
-------------------------
.. automodule:: migen.genlib.sort

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.. _simulating:
Simulating a Migen design
#########################
Migen allows you to easily simulate your FHDL design and interface it with arbitrary Python code.
Migen allows you to easily simulate your FHDL design and interface it with arbitrary Python code. The simulator is written in pure Python and interprets the FHDL structure directly without using an external Verilog simulator.
To interpret the design, the FHDL structure is simply converted into Verilog and then simulated using an external program (e.g. Icarus Verilog). This is is intrinsically compatible with VHDL/Verilog instantiations from Migen and maximizes software reuse.
To interface the external simulator to Python, a VPI task is called at each clock cycle and implement the test bench functionality proper - which can be fully written in Python.
Signals inside the simulator can be read and written using VPI as well. This is how the Python test bench generates stimulus and obtains the values of signals for processing.
.. _vpisetup:
Installing the VPI module
*************************
To communicate with the external simulator, Migen uses a UNIX domain socket and a custom protocol which is handled by a VPI plug-in (written in C) on the simulator side.
To build and install this plug-in, run the following commands from the ``vpi`` directory: ::
make [INCDIRS=-I/usr/...]
make install [INSTDIR=/usr/...]
The variable ``INCDIRS`` (default: empty) can be used to give a list of paths where to search for the include files. This is useful considering that different Linux distributions put the ``vpi_user.h`` file in various locations.
The variable ``INSTDIR`` (default: ``/usr/lib/ivl``) specifies where the ``migensim.vpi`` file is to be installed.
This plug-in is designed for Icarus Verilog, but can probably be used with most Verilog simulators with minor modifications.
The generic simulator object
****************************
The generic simulator object (``migen.sim.generic.Simulator``) is the central component of the simulation.
Creating a simulator object
===========================
The constructor of the ``Simulator`` object takes the following parameters:
#. The module to simulate.
#. A top-level object (see :ref:`toplevel`). With the default value of ``None``, the simulator creates a default top-level object itself.
#. A simulator runner object (see :ref:`simrunner`). With the default value of ``None``, Icarus Verilog is used with the default parameters.
#. The name of the UNIX domain socket used to communicate with the external simulator through the VPI plug-in (default: "simsocket").
#. Additional keyword arguments (if any) are passed to the Verilog conversion function.
For proper initialization and clean-up, the simulator object should be used as a context manager, e.g. ::
with Simulator(tb) as s:
s.run()
Running the simulation
======================
Running the simulation is achieved by calling the ``run`` method of the ``Simulator`` object.
It takes an optional parameter ``ncycles`` that defines the maximum number of clock cycles that this call simulates. The default value of ``None`` sets no cycle limit.
The cycle counter
=================
Simulation functions can read the current simulator cycle by reading the ``cycle_counter`` property of the ``Simulator``. The cycle counter's value is 0 for the cycle immediately following the reset cycle.
Simplified simulation set-up
============================
Most simulations are run in the same way and do not need the slightly heavy syntax needed to create and run a Simulator object. There is a function that exposes the most common features with a simpler syntax: ::
run_simulation(module, ncycles=None, vcd_name=None, keep_files=False)
Module-level simulation API
***************************
Simulation functions and generators
===================================
Whenever a ``Module`` declares a ``do_simulation`` method, it is executed at each cycle and can manipulate values from signal and memories (as explained in the next section).
Instead of defining such a method, ``Modules`` can declare a ``gen_simulation`` generator that is initialized at the beginning of the simulation, and yields (usually multiple times) to proceed to the next simulation cycle.
Simulation generators can yield an integer in order to wait for that number of cycles, or yield nothing (``None``) to wait for 1 cycle.
Reading and writing values
===========================
Simulation functions and generators take as parameter a special object that gives access to the values of the signals of the current module using the regular Python read/write syntax. Nested objects, lists and dictionaries containing signals are supported, as well as Migen memories, for reading and writing.
Here are some examples: ::
def do_simulation(self, selfp):
selfp.foo = 42
self.last_foo_value = selfp.foo
selfp.dut.banks[2].bar["foo"] = 1
self.last_memory_data = selfp.dut.mem[self.memory_index]
The semantics of reads and writes (respectively immediately before and after the clock edge) match those of the non-blocking assignment in Verilog. Note that because of Verilog's design, reading "variable" signals (i.e. written to using blocking assignment) directly may give unexpected and non-deterministic results and is not supported. You should instead read the values of variables after they have gone through a non-blocking assignment in the same ``always`` block.
Those constructs are syntactic sugar for calling the ``Simulator`` object's methods ``rd`` and ``wr``, that respectively read and write data from and to the simulated design. The simulator object can be accessed as ``selfp.simulator``, and for special cases it is sometimes desirable to call the lower-level methods directly.
The ``rd`` method takes the FHDL ``Signal`` object to read and returns its value as a Python integer. The returned integer is the value of the signal immediately before the clock edge.
The ``wr`` method takes a ``Signal`` object and the value to write as a Python integer. The signal takes the new value immediately after the clock edge.
References to FHDL ``Memory`` objects can also be passed to the ``rd`` and ``wr`` methods. In this case, they take an additional parameter for the memory address.
Simulation termination management
=================================
Simulation functions and generators can raise the ``StopSimulation`` exception. It is automatically raised when a simulation generator is exhausted. This exception disables the current simulation function, i.e. it is no longer run by the simulator. The simulation is over when all simulation functions are disabled (or the specified maximum number of cycles, if any, has been reached - whichever comes first).
Some simulation modules only respond to external stimuli - e.g. the ``bus.wishbone.Tap`` that snoops on bus transactions and prints them on the console - and have simulation functions that never end. To deal with those, the new API introduces "passive" simulation functions that are not taken into account when deciding to continue to run the simulation. A simulation function is declared passive by setting a "passive" attribute on it that evaluates to True. Raising ``StopSimulation`` in such a function still makes the simulator stop running it for the rest of the simulation.
When starting the simulation of a design that contains no simulation functions or only passive simulation functions, the simulation will continue until the specified number of cycles is reached. The ``ncycles`` parameter is mandatory in this case.
.. _simrunner:
The external simulator runner
*****************************
Role
====
The runner object is responsible for starting the external simulator, loading the VPI module, and feeding the generated Verilog into the simulator.
It must implement a ``start`` method, called by the ``Simulator``, which takes two strings as parameters. They contain respectively the Verilog source of the top-level design and the converted module.
Icarus Verilog support
======================
Migen comes with a ``migen.sim.icarus.Runner`` object that supports Icarus Verilog.
Its constructor has the following optional parameters:
#. ``extra_files`` (default: ``None``): lists additional Verilog files to simulate.
#. ``top_file`` (default: "migensim_top.v"): name of the temporary file containing the top-level.
#. ``dut_file`` (default: "migensim_dut.v"): name of the temporary file containing the converted fragment.
#. ``vvp_file`` (default: ``None``): name of the temporary file compiled by Icarus Verilog. When ``None``, becomes ``dut_file + "vp"``.
#. ``keep_files`` (default: ``False``): do not delete temporary files. Useful for debugging.
.. _toplevel:
The top-level object
********************
Role of the top-level object
============================
The top-level object is responsible for generating the Verilog source for the top-level test bench.
It must implement a method ``get`` that takes as parameter the name of the UNIX socket the VPI plugin should connect to, and returns the full Verilog source as a string.
It must have the following attributes (which are read by the ``Simulator`` object):
* ``clk_name``: name of the clock signal.
* ``rst_name``: name of the reset signal.
* ``dut_type``: module type of the converted fragment.
* ``dut_name``: name used for instantiating the converted fragment.
* ``top_name``: name/module type of the top-level design.
Role of the generated Verilog
=============================
The generated Verilog must:
#. instantiate the converted fragment and connect its clock and reset ports.
#. produce a running clock signal.
#. assert the reset signal for the first cycle and deassert it immediately after.
#. at the beginning, call the task ``$migensim_connect`` with the UNIX socket name as parameter.
#. at each rising clock edge, call the task ``$migensim_tick``. It is an error to call ``$migensim_tick`` before a call to ``$migensim_connect``.
#. set up the optional VCD output file.
The generic top-level object
============================
Migen comes with a ``migen.sim.generic.TopLevel`` object that implements the above behaviour. It should be usable in the majority of cases.
The main parameters of its constructor are the output VCD file (default: ``None``) and the levels of hierarchy that must be present in the VCD (default: 1).
[To be rewritten]

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Synthesizing a Migen design
###########################
[To be written]

5
examples/basic/arrays.py
View file

@ -1,4 +1,4 @@
from migen.fhdl.std import *
from migen import *
from migen.fhdl import verilog
@ -24,4 +24,5 @@ class Example(Module):
outa = Array(Signal() for a in range(dy))
self.specials += Instance("test", o_O=outa[y], i_I=ina[x])
print(verilog.convert(Example()))
if __name__ == "__main__":
print(verilog.convert(Example()))

20
examples/basic/complex.py
View file

@ -1,20 +0,0 @@
from migen.fhdl.std import *
from migen.genlib.complex import *
from migen.fhdl import verilog
class Example(Module):
def __init__(self):
w = Complex(32, 42)
A = SignalC(16)
B = SignalC(16)
Bw = SignalC(16)
C = SignalC(16)
D = SignalC(16)
self.comb += Bw.eq(B*w)
self.sync += [
C.eq(A + Bw),
D.eq(A - Bw)
]
print(verilog.convert(Example()))

11
examples/basic/fsm.py
View file

@ -1,12 +1,11 @@
from migen.fhdl.std import *
from migen import *
from migen.fhdl import verilog
from migen.genlib.fsm import FSM, NextState, NextValue
class Example(Module):
def __init__(self):
self.s = Signal()
self.counter = Signal(8)
x = Array(Signal(name="a") for i in range(7))
myfsm = FSM()
self.submodules += myfsm
@ -18,6 +17,7 @@ class Example(Module):
myfsm.act("BAR",
self.s.eq(0),
NextValue(self.counter, self.counter + 1),
NextValue(x[self.counter], 89),
NextState("FOO")
)
@ -26,5 +26,6 @@ class Example(Module):
self.bl = myfsm.before_leaving("FOO")
self.al = myfsm.after_leaving("FOO")
example = Example()
print(verilog.convert(example, {example.s, example.counter, example.be, example.ae, example.bl, example.al}))
if __name__ == "__main__":
example = Example()
print(verilog.convert(example, {example.s, example.counter, example.be, example.ae, example.bl, example.al}))

22
examples/basic/graycounter.py
View file

@ -1,20 +1,18 @@
from random import Random
from migen.fhdl.std import *
from migen import *
from migen.genlib.cdc import GrayCounter
from migen.sim.generic import run_simulation
class TB(Module):
def __init__(self, width=3):
self.width = width
self.submodules.gc = GrayCounter(self.width)
self.prng = Random(7345)
def tb(dut):
prng = Random(7345)
for i in range(35):
print("{0:0{1}b} CE={2} bin={3}".format((yield dut.q),
len(dut.q), (yield dut.ce), (yield dut.q_binary)))
yield dut.ce.eq(prng.getrandbits(1))
yield
def do_simulation(self, selfp):
print("{0:0{1}b} CE={2} bin={3}".format(selfp.gc.q,
self.width, selfp.gc.ce, selfp.gc.q_binary))
selfp.gc.ce = self.prng.getrandbits(1)
if __name__ == "__main__":
run_simulation(TB(), ncycles=35)
dut = GrayCounter(3)
run_simulation(dut, tb(dut), vcd_name="graycounter.vcd")

37
examples/basic/hamming.py
View file

@ -1,37 +0,0 @@
from migen.fhdl import verilog
from migen.fhdl.std import *
from migen.genlib.mhamgen import HammingGenerator, HammingChecker
# Instantiates Hamming code generator and checker modules back
# to back. Also creates an intermediate bus between generator
# and checker and injects a single-bit error on the bus, to
# demonstrate the correction.
class gen_check(Module):
def __init__(self, width=8):
# Save module parameters and instantiate generator and checker
self.width = width
hg = HammingGenerator(self.width)
hc = HammingChecker(self.width, correct=True)
self.submodules += hg
self.submodules += hc
# Create the intermediate bus and inject a single-bit error on
# the bus. Position of the error bit is controllable by the
# error_bit input.
data = Signal(width)
error_bit = Signal(bits_for(width))
self.comb += data.eq(hg.data_in ^ (1 << error_bit))
self.comb += hc.code_in.eq(hg.code_out)
self.comb += hc.data_in.eq(data)
# Call out I/O necessary for testing the generator/checker
self.io = set()
self.io.add(hg.data_in)
self.io.add(hc.enable)
self.io.add(error_bit)
self.io.add(hc.code_out)
self.io.add(hc.data_out)
gc = gen_check()
print(verilog.convert(gc, gc.io, name="gen_check"))

3
examples/basic/instance.py
View file

@ -1,7 +1,6 @@
import subprocess
from migen.fhdl.std import *
from migen.fhdl.specials import Instance
from migen import *
from migen.fhdl.verilog import convert

7
examples/basic/local_cd.py
View file

@ -1,4 +1,4 @@
from migen.fhdl.std import *
from migen import *
from migen.fhdl import verilog
from migen.genlib.divider import Divider
@ -14,5 +14,6 @@ class MultiMod(Module):
self.submodules.foo = CDM()
self.submodules.bar = CDM()
mm = MultiMod()
print(verilog.convert(mm, {mm.foo.cd_sys.clk, mm.bar.cd_sys.clk}))
if __name__ == "__main__":
mm = MultiMod()
print(verilog.convert(mm, {mm.foo.cd_sys.clk, mm.bar.cd_sys.clk}))

8
examples/basic/memory.py
View file

@ -1,4 +1,4 @@
from migen.fhdl.std import *
from migen import *
from migen.fhdl import verilog
@ -11,5 +11,7 @@ class Example(Module):
self.ios = {p1.adr, p1.dat_r, p1.we, p1.dat_w,
p2.adr, p2.dat_r, p2.re}
example = Example()
print(verilog.convert(example, example.ios))
if __name__ == "__main__":
example = Example()
print(verilog.convert(example, example.ios))

8
examples/basic/namer.py
View file

@ -1,6 +1,8 @@
from migen.fhdl.std import *
from migen import *
from migen.fhdl import verilog
from migen.genlib.misc import optree
from functools import reduce
from operator import or_
def gen_list(n):
@ -37,6 +39,6 @@ class Example(Module):
for lst in [a, b, c]:
for obj in lst:
allsigs.extend(obj.sigs)
self.comb += output.eq(optree("|", allsigs))
self.comb += output.eq(reduce(or_, allsigs))
print(verilog.convert(Example()))

10
examples/basic/psync.py
View file

@ -1,4 +1,4 @@
from migen.fhdl.std import *
from migen import *
from migen.fhdl.specials import SynthesisDirective
from migen.fhdl import verilog
from migen.genlib.cdc import *
@ -16,6 +16,8 @@ class XilinxMultiReg:
def lower(dr):
return XilinxMultiRegImpl(dr.i, dr.o, dr.odomain, dr.n)
ps = PulseSynchronizer("from", "to")
v = verilog.convert(ps, {ps.i, ps.o}, special_overrides={MultiReg: XilinxMultiReg})
print(v)
if __name__ == "__main__":
ps = PulseSynchronizer("from", "to")
v = verilog.convert(ps, {ps.i, ps.o}, special_overrides={MultiReg: XilinxMultiReg})
print(v)

12
examples/basic/record.py
View file

@ -1,6 +1,6 @@
from migen.fhdl.std import *
from migen import *
from migen.fhdl import verilog
from migen.genlib.record import *
L = [
("position", [
@ -19,6 +19,8 @@ class Test(Module):
slave = Record(L)
self.comb += master.connect(slave)
print(verilog.convert(Test()))
print(layout_len(L))
print(layout_partial(L, "position/x", "color"))
if __name__ == "__main__":
print(verilog.convert(Test()))
print(layout_len(L))
print(layout_partial(L, "position/x", "color"))

6
examples/basic/reslice.py
View file

@ -1,4 +1,4 @@
from migen.fhdl.std import *
from migen import *
from migen.fhdl import verilog
@ -14,4 +14,6 @@ class Example(Module):
self.comb += s3.eq(0)
self.comb += d.eq(Cat(d[::-1], Cat(s1[:1], s3[-4:])[:3]))
print(verilog.convert(Example()))
if __name__ == "__main__":
print(verilog.convert(Example()))

29
examples/basic/simple_gpio.py
View file

@ -1,29 +0,0 @@
from migen.fhdl.std import *
from migen.fhdl import verilog
from migen.genlib.cdc import MultiReg
from migen.bank import description, csrgen
class Example(Module):
def __init__(self, ninputs=32, noutputs=32):
r_o = description.CSRStorage(noutputs, atomic_write=True)
r_i = description.CSRStatus(ninputs)
self.submodules.bank = csrgen.Bank([r_o, r_i])
self.gpio_in = Signal(ninputs)
self.gpio_out = Signal(ninputs)
###
gpio_in_s = Signal(ninputs)
self.specials += MultiReg(self.gpio_in, gpio_in_s)
self.comb += [
self.gpio_out.eq(r_o.storage),
r_i.status.eq(gpio_in_s)
]
example = Example()
i = example.bank.bus
v = verilog.convert(example, {i.dat_r, i.adr, i.we, i.dat_w,
example.gpio_in, example.gpio_out})
print(v)

7
examples/basic/tristate.py
View file

@ -1,4 +1,4 @@
from migen.fhdl.std import *
from migen import *
from migen.fhdl import verilog
@ -8,5 +8,6 @@ class Example(Module):
self.t = TSTriple(n)
self.specials += self.t.get_tristate(self.pad)
e = Example()
print(verilog.convert(e, ios={e.pad, e.t.o, e.t.oe, e.t.i}))
if __name__ == "__main__":
e = Example()
print(verilog.convert(e, ios={e.pad, e.t.o, e.t.oe, e.t.i}))

7
examples/basic/two_dividers.py
View file

@ -1,4 +1,4 @@
from migen.fhdl.std import *
from migen import *
from migen.fhdl import verilog
from migen.genlib import divider
@ -14,5 +14,6 @@ class Example(Module):
d1.ready_o, d1.quotient_o, d1.remainder_o, d1.start_i, d1.dividend_i, d1.divisor_i,
d2.ready_o, d2.quotient_o, d2.remainder_o, d2.start_i, d2.dividend_i, d2.divisor_i}
example = Example(16)
print(verilog.convert(example, example.ios | {example.ce, example.reset}))
if __name__ == "__main__":
example = Example(16)
print(verilog.convert(example, example.ios | {example.ce, example.reset}))

105
examples/dataflow/dma.py
View file

@ -1,105 +0,0 @@
from random import Random
from migen.fhdl.std import *
from migen.flow.network import *
from migen.flow.transactions import *
from migen.actorlib import dma_wishbone
from migen.actorlib.sim import *
from migen.bus import wishbone
from migen.sim.generic import run_simulation
class MyModel:
def read(self, address):
return address + 4
class MyModelWB(MyModel, wishbone.TargetModel):
def __init__(self):
self.prng = Random(763627)
def can_ack(self, bus):
return self.prng.randrange(0, 2)
def adrgen_gen():
for i in range(10):
print("Address: " + hex(i))
yield Token("address", {"a": i})
class SimAdrGen(SimActor):
def __init__(self, nbits):
self.address = Source([("a", nbits)])
SimActor.__init__(self, adrgen_gen())
def dumper_gen():
while True:
t = Token("data", idle_wait=True)
yield t
print("Received: " + hex(t.value["d"]))
class SimDumper(SimActor):
def __init__(self):
self.data = Sink([("d", 32)])
SimActor.__init__(self, dumper_gen())
def trgen_gen():
for i in range(10):
a = i
d = i+10
print("Address: " + hex(a) + " Data: " + hex(d))
yield Token("address_data", {"a": a, "d": d})
class SimTrGen(SimActor):
def __init__(self, a_nbits):
self.address_data = Source([("a", a_nbits), ("d", 32)])
SimActor.__init__(self, trgen_gen())
class TBWishbone(Module):
def __init__(self, master):
self.submodules.peripheral = wishbone.Target(MyModelWB())
self.submodules.tap = wishbone.Tap(self.peripheral.bus)
self.submodules.interconnect = wishbone.InterconnectPointToPoint(master.bus,
self.peripheral.bus)
class TBWishboneReader(TBWishbone):
def __init__(self):
self.adrgen = SimAdrGen(30)
self.reader = dma_wishbone.Reader()
self.dumper = SimDumper()
g = DataFlowGraph()
g.add_connection(self.adrgen, self.reader)
g.add_connection(self.reader, self.dumper)
self.submodules.comp = CompositeActor(g)
TBWishbone.__init__(self, self.reader)
class TBWishboneWriter(TBWishbone):
def __init__(self):
self.trgen = SimTrGen(30)
self.writer = dma_wishbone.Writer()
g = DataFlowGraph()
g.add_connection(self.trgen, self.writer)
self.submodules.comp = CompositeActor(g)
TBWishbone.__init__(self, self.writer)
def test_wb_reader():
print("*** Testing Wishbone reader")
run_simulation(TBWishboneReader(), 100)
def test_wb_writer():
print("*** Testing Wishbone writer")
run_simulation(TBWishboneWriter(), 100)
if __name__ == "__main__":
test_wb_reader()
test_wb_writer()

41
examples/dataflow/misc.py
View file

@ -1,41 +0,0 @@
from migen.flow.network import *
from migen.flow.transactions import *
from migen.actorlib import misc
from migen.actorlib.sim import *
from migen.sim.generic import run_simulation
def source_gen():
for i in range(10):
v = i + 5
print("==> " + str(v))
yield Token("source", {"maximum": v})
class SimSource(SimActor):
def __init__(self):
self.source = Source([("maximum", 32)])
SimActor.__init__(self, source_gen())
def sink_gen():
while True:
t = Token("sink")
yield t
print(t.value["value"])
class SimSink(SimActor):
def __init__(self):
self.sink = Sink([("value", 32)])
SimActor.__init__(self, sink_gen())
if __name__ == "__main__":
source = SimSource()
loop = misc.IntSequence(32)
sink = SimSink()
g = DataFlowGraph()
g.add_connection(source, loop)
g.add_connection(loop, sink)
comp = CompositeActor(g)
run_simulation(comp, ncycles=500)

73
examples/dataflow/structuring.py
View file

@ -1,73 +0,0 @@
from itertools import count
import networkx as nx
import matplotlib.pyplot as plt
from migen.flow.network import *
from migen.flow.transactions import *
from migen.actorlib import structuring
from migen.actorlib.sim import *
from migen.flow import perftools
from migen.sim.generic import run_simulation
pack_factor = 5
base_layout = [("value", 32)]
packed_layout = structuring.pack_layout(base_layout, pack_factor)
rawbits_layout = [("value", 32*pack_factor)]
def source_gen():
for i in count(0):
yield Token("source", {"value": i})
class SimSource(SimActor):
def __init__(self):
self.source = Source(base_layout)
SimActor.__init__(self, source_gen())
def sink_gen():
while True:
t = Token("sink")
yield t
print(t.value["value"])
class SimSink(SimActor):
def __init__(self):
self.sink = Sink(base_layout)
SimActor.__init__(self, sink_gen())
class TB(Module):
def __init__(self):
source = SimSource()
sink = SimSink()
# A tortuous way of passing integer tokens.
packer = structuring.Pack(base_layout, pack_factor)
to_raw = structuring.Cast(packed_layout, rawbits_layout)
from_raw = structuring.Cast(rawbits_layout, packed_layout)
unpacker = structuring.Unpack(pack_factor, base_layout)
self.g = DataFlowGraph()
self.g.add_connection(source, packer)
self.g.add_connection(packer, to_raw)
self.g.add_connection(to_raw, from_raw)
self.g.add_connection(from_raw, unpacker)
self.g.add_connection(unpacker, sink)
self.submodules.comp = CompositeActor(self.g)
self.submodules.reporter = perftools.DFGReporter(self.g)
if __name__ == "__main__":
tb = TB()
run_simulation(tb, ncycles=1000)
g = nx.MultiDiGraph()
for u, v, edge in tb.g.edges_iter():
g.add_edge(u, v, **edge)
g_layout = nx.spectral_layout(g)
nx.draw(g, g_layout)
nx.draw_networkx_edge_labels(g, g_layout, tb.reporter.get_edge_labels())
plt.show()

84
examples/sim/abstract_transactions_wb.py
View file

@ -1,84 +0,0 @@
from random import Random
from migen.fhdl.std import *
from migen.bus.transactions import *
from migen.bus import wishbone
from migen.sim.generic import run_simulation
# Our bus master.
# Python generators let us program bus transactions in an elegant sequential style.
def my_generator():
prng = Random(92837)
# Write to the first addresses.
for x in range(10):
t = TWrite(x, 2*x)
yield t
print("Wrote in " + str(t.latency) + " cycle(s)")
# Insert some dead cycles to simulate bus inactivity.
for delay in range(prng.randrange(0, 3)):
yield None
# Read from the first addresses.
for x in range(10):
t = TRead(x)
yield t
print("Read " + str(t.data) + " in " + str(t.latency) + " cycle(s)")
for delay in range(prng.randrange(0, 3)):
yield None
# Our bus slave.
class MyModelWB(wishbone.TargetModel):
def __init__(self):
self.prng = Random(763627)
def read(self, address):
return address + 4
def can_ack(self, bus):
# Simulate variable latency.
return self.prng.randrange(0, 2)
class TB(Module):
def __init__(self):
# The "wishbone.Initiator" library component runs our generator
# and manipulates the bus signals accordingly.
self.submodules.master = wishbone.Initiator(my_generator())
# The "wishbone.Target" library component examines the bus signals
# and calls into our model object.
self.submodules.slave = wishbone.Target(MyModelWB())
# The "wishbone.Tap" library component examines the bus at the slave port
# and displays the transactions on the console (<TRead...>/<TWrite...>).
self.submodules.tap = wishbone.Tap(self.slave.bus)
# Connect the master to the slave.
self.submodules.intercon = wishbone.InterconnectPointToPoint(self.master.bus, self.slave.bus)
if __name__ == "__main__":
run_simulation(TB())
# Output:
# <TWrite adr:0x0 dat:0x0>
# Wrote in 0 cycle(s)
# <TWrite adr:0x1 dat:0x2>
# Wrote in 0 cycle(s)
# <TWrite adr:0x2 dat:0x4>
# Wrote in 0 cycle(s)
# <TWrite adr:0x3 dat:0x6>
# Wrote in 1 cycle(s)
# <TWrite adr:0x4 dat:0x8>
# Wrote in 1 cycle(s)
# <TWrite adr:0x5 dat:0xa>
# Wrote in 2 cycle(s)
# ...
# <TRead adr:0x0 dat:0x4>
# Read 4 in 2 cycle(s)
# <TRead adr:0x1 dat:0x5>
# Read 5 in 2 cycle(s)
# <TRead adr:0x2 dat:0x6>
# Read 6 in 1 cycle(s)
# <TRead adr:0x3 dat:0x7>
# Read 7 in 1 cycle(s)
# ...

32
examples/sim/basic1.py
View file

@ -1,9 +1,7 @@
from migen.fhdl.std import *
from migen.sim.generic import run_simulation
from migen import *
# Our simple counter, which increments at every cycle
# and prints its current value in simulation.
# Our simple counter, which increments at every cycle.
class Counter(Module):
def __init__(self):
self.count = Signal(4)
@ -12,18 +10,20 @@ class Counter(Module):
# We do it with convertible/synthesizable FHDL code.
self.sync += self.count.eq(self.count + 1)
# This function will be called at every cycle.
def do_simulation(self, selfp):
# Simply read the count signal and print it.
# The output is:
# Count: 0
# Count: 1
# Count: 2
# ...
print("Count: " + str(selfp.count))
# Simply read the count signal and print it.
# The output is:
# Count: 0
# Count: 1
# Count: 2
# ...
def counter_test(dut):
for i in range(20):
print((yield dut.count)) # read and print
yield # next clock cycle
# simulation ends with this generator
if __name__ == "__main__":
dut = Counter()
# Since we do not use StopSimulation, limit the simulation
# to some number of cycles.
run_simulation(dut, ncycles=20)
run_simulation(dut, counter_test(dut), vcd_name="basic1.vcd")

20
examples/sim/basic2.py
View file

@ -1,5 +1,4 @@
from migen.fhdl.std import *
from migen.sim.generic import run_simulation
from migen import *
# A slightly more elaborate counter.
@ -13,15 +12,17 @@ class Counter(Module):
self.sync += If(self.ce, self.count.eq(self.count + 1))
def do_simulation(self, selfp):
def counter_test(dut):
for cycle in range(20):
# Only assert CE every second cycle.
# => each counter value is held for two cycles.
if selfp.simulator.cycle_counter % 2:
selfp.ce = 0 # This is how you write to a signal.
if cycle % 2:
yield dut.ce.eq(0) # This is how you write to a signal.
else:
selfp.ce = 1
print("Cycle: " + str(selfp.simulator.cycle_counter) + " Count: " + \
str(selfp.count))
yield dut.ce.eq(1)
print("Cycle: {} Count: {}".format(cycle, (yield dut.count)))
yield
# Output is:
# Cycle: 0 Count: -5
@ -33,5 +34,4 @@ class Counter(Module):
if __name__ == "__main__":
dut = Counter()
# Demonstrate VCD output
run_simulation(dut, vcd_name="my.vcd", ncycles=20)
run_simulation(dut, counter_test(dut), vcd_name="basic2.vcd")

47
examples/sim/dataflow.py
View file

@ -1,47 +0,0 @@
from migen.fhdl.std import *
from migen.flow.actor import *
from migen.flow.transactions import *
from migen.flow.network import *
from migen.actorlib.sim import *
from migen.sim.generic import run_simulation
def source_gen():
for i in range(10):
print("Sending: " + str(i))
yield Token("source", {"value": i})
class SimSource(SimActor):
def __init__(self):
self.source = Source([("value", 32)])
SimActor.__init__(self, source_gen())
def sink_gen():
while True:
t = Token("sink")
yield t
print("Received: " + str(t.value["value"]))
class SimSink(SimActor):
def __init__(self):
self.sink = Sink([("value", 32)])
SimActor.__init__(self, sink_gen())
class TB(Module):
def __init__(self):
self.source = SimSource()
self.sink = SimSink()
g = DataFlowGraph()
g.add_connection(self.source, self.sink)
self.submodules.comp = CompositeActor(g)
def do_simulation(self, selfp):
if self.source.token_exchanger.done:
raise StopSimulation
if __name__ == "__main__":
run_simulation(TB())

38
examples/sim/fir.py
View file

@ -1,11 +1,12 @@
from functools import reduce
from operator import add
from math import cos, pi
from scipy import signal
import matplotlib.pyplot as plt
from migen.fhdl.std import *
from migen import *
from migen.fhdl import verilog
from migen.genlib.misc import optree
from migen.sim.generic import run_simulation
# A synthesizable FIR filter.
@ -27,25 +28,21 @@ class FIR(Module):
c_fp = int(c*2**(self.wsize - 1))
muls.append(c_fp*sreg)
sum_full = Signal((2*self.wsize-1, True))
self.sync += sum_full.eq(optree("+", muls))
self.comb += self.o.eq(sum_full[self.wsize-1:])
self.sync += sum_full.eq(reduce(add, muls))
self.comb += self.o.eq(sum_full >> self.wsize-1)
# A test bench for our FIR filter.
# Generates a sine wave at the input and records the output.
class TB(Module):
def __init__(self, coef, frequency):
self.submodules.fir = FIR(coef)
self.frequency = frequency
self.inputs = []
self.outputs = []
def fir_tb(dut, frequency, inputs, outputs):
f = 2**(dut.wsize - 1)
for cycle in range(200):
v = 0.1*cos(2*pi*frequency*cycle)
yield dut.i.eq(int(f*v))
inputs.append(v)
outputs.append((yield dut.o)/f)
yield
def do_simulation(self, selfp):
f = 2**(self.fir.wsize - 1)
v = 0.1*cos(2*pi*self.frequency*selfp.simulator.cycle_counter)
selfp.fir.i = int(f*v)
self.inputs.append(v)
self.outputs.append(selfp.fir.o/f)
if __name__ == "__main__":
# Compute filter coefficients with SciPy.
@ -56,10 +53,9 @@ if __name__ == "__main__":
in_signals = []
out_signals = []
for frequency in [0.05, 0.1, 0.25]:
tb = TB(coef, frequency)
run_simulation(tb, ncycles=200)
in_signals += tb.inputs
out_signals += tb.outputs
dut = FIR(coef)
tb = fir_tb(dut, frequency, in_signals, out_signals)
run_simulation(dut, tb)
# Plot data from the input and output waveforms.
plt.plot(in_signals)

30
examples/sim/memory.py
View file

@ -1,5 +1,4 @@
from migen.fhdl.std import *
from migen.sim.generic import run_simulation
from migen import *
class Mem(Module):
@ -8,19 +7,20 @@ class Mem(Module):
# from 0 to 19.
self.specials.mem = Memory(16, 2**12, init=list(range(20)))
def do_simulation(self, selfp):
# Read the memory. Use the cycle counter as address.
value = selfp.mem[selfp.simulator.cycle_counter]
# Print the result. Output is:
# 0
# 1
# 2
# ...
def memory_test(dut):
# write (only first 5 values)
for i in range(5):
yield dut.mem[i].eq(42 + i)
# remember: values are written after the tick, and read before the tick.
# wait one tick for the memory to update.
yield
# read what we have written, plus some initialization data
for i in range(10):
value = yield dut.mem[i]
print(value)
# Raising StopSimulation disables the current (and here, only one)
# simulation function. Simulator stops when all functions are disabled.
if value == 10:
raise StopSimulation
if __name__ == "__main__":
run_simulation(Mem())
dut = Mem()
run_simulation(dut, memory_test(dut))

2
mibuild/altera/__init__.py
View file

@ -1,2 +0,0 @@
from mibuild.altera.platform import AlteraPlatform
from mibuild.altera.programmer import USBBlaster

2
mibuild/lattice/__init__.py
View file

@ -1,2 +0,0 @@
from mibuild.lattice.platform import LatticePlatform
from mibuild.lattice.programmer import LatticeProgrammer

1
mibuild/sim/__init__.py
View file

@ -1 +0,0 @@
from mibuild.sim.platform import SimPlatform

2
mibuild/xilinx/__init__.py
View file

@ -1,2 +0,0 @@
from mibuild.xilinx.platform import XilinxPlatform
from mibuild.xilinx.programmer import UrJTAG, XC3SProg, FpgaProg, VivadoProgrammer, iMPACT, Adept

10
migen/__init__.py
View file

@ -0,0 +1,10 @@
from migen.fhdl.structure import *
from migen.fhdl.module import *
from migen.fhdl.specials import *
from migen.fhdl.bitcontainer import *
from migen.fhdl.decorators import *
from migen.sim import *
from migen.genlib.record import *
from migen.genlib.fsm import *

0
migen/actorlib/__init__.py
View file

56
migen/actorlib/dma_wishbone.py
View file

@ -1,56 +0,0 @@
from migen.fhdl.std import *
from migen.bus import wishbone
from migen.flow.actor import *
class Reader(Module):
def __init__(self):
self.bus = wishbone.Interface()
self.address = Sink([("a", 30)])
self.data = Source([("d", 32)])
self.busy = Signal()
###
bus_stb = Signal()
data_reg_loaded = Signal()
data_reg = Signal(32)
self.comb += [
self.busy.eq(data_reg_loaded),
self.bus.we.eq(0),
bus_stb.eq(self.address.stb & (~data_reg_loaded | self.data.ack)),
self.bus.cyc.eq(bus_stb),
self.bus.stb.eq(bus_stb),
self.bus.adr.eq(self.address.a),
self.address.ack.eq(self.bus.ack),
self.data.stb.eq(data_reg_loaded),
self.data.d.eq(data_reg)
]
self.sync += [
If(self.data.ack, data_reg_loaded.eq(0)),
If(self.bus.ack,
data_reg_loaded.eq(1),
data_reg.eq(self.bus.dat_r)
)
]
class Writer(Module):
def __init__(self):
self.bus = wishbone.Interface()
self.address_data = Sink([("a", 30), ("d", 32)])
self.busy = Signal()
###
self.comb += [
self.busy.eq(0),
self.bus.we.eq(1),
self.bus.cyc.eq(self.address_data.stb),
self.bus.stb.eq(self.address_data.stb),
self.bus.adr.eq(self.address_data.a),
self.bus.sel.eq(0xf),
self.bus.dat_w.eq(self.address_data.d),
self.address_data.ack.eq(self.bus.ack)
]

57
migen/actorlib/fifo.py
View file

@ -1,57 +0,0 @@
from migen.fhdl.std import *
from migen.flow.actor import *
from migen.genlib import fifo
class _FIFOActor(Module):
def __init__(self, fifo_class, layout, depth):
self.sink = Sink(layout)
self.source = Source(layout)
self.busy = Signal()
###
description = self.sink.description
fifo_layout = [
("payload", description.payload_layout),
# Note : Can be optimized by passing parameters
# in another fifo. We will only have one
# data per packet.
("param", description.param_layout)
]
if description.packetized:
fifo_layout += [("sop", 1), ("eop", 1)]
self.submodules.fifo = fifo_class(fifo_layout, depth)
self.comb += [
self.sink.ack.eq(self.fifo.writable),
self.fifo.we.eq(self.sink.stb),
self.fifo.din.payload.eq(self.sink.payload),
self.fifo.din.param.eq(self.sink.param),
self.source.stb.eq(self.fifo.readable),
self.source.payload.eq(self.fifo.dout.payload),
self.source.param.eq(self.fifo.dout.param),
self.fifo.re.eq(self.source.ack)
]
if description.packetized:
self.comb += [
self.fifo.din.sop.eq(self.sink.sop),
self.fifo.din.eop.eq(self.sink.eop),
self.source.sop.eq(self.fifo.dout.sop),
self.source.eop.eq(self.fifo.dout.eop)
]
class SyncFIFO(_FIFOActor):
def __init__(self, layout, depth, buffered=False):
_FIFOActor.__init__(
self,
fifo.SyncFIFOBuffered if buffered else fifo.SyncFIFO,
layout, depth)
class AsyncFIFO(_FIFOActor):
def __init__(self, layout, depth):
_FIFOActor.__init__(self, fifo.AsyncFIFO, layout, depth)

96
migen/actorlib/misc.py
View file

@ -1,96 +0,0 @@
from migen.fhdl.std import *
from migen.genlib.record import *
from migen.genlib.fsm import *
from migen.flow.actor import *
from migen.flow.plumbing import Buffer
# Generates integers from start to maximum-1
class IntSequence(Module):
def __init__(self, nbits, offsetbits=0, step=1):
parameters_layout = [("maximum", nbits)]
if offsetbits:
parameters_layout.append(("offset", offsetbits))
self.parameters = Sink(parameters_layout)
self.source = Source([("value", max(nbits, offsetbits))])
self.busy = Signal()
###
load = Signal()
ce = Signal()
last = Signal()
maximum = Signal(nbits)
if offsetbits:
offset = Signal(offsetbits)
counter = Signal(nbits)
if step > 1:
self.comb += last.eq(counter + step >= maximum)
else:
self.comb += last.eq(counter + 1 == maximum)
self.sync += [
If(load,
counter.eq(0),
maximum.eq(self.parameters.maximum),
offset.eq(self.parameters.offset) if offsetbits else None
).Elif(ce,
If(last,
counter.eq(0)
).Else(
counter.eq(counter + step)
)
)
]
if offsetbits:
self.comb += self.source.value.eq(counter + offset)
else:
self.comb += self.source.value.eq(counter)
fsm = FSM()
self.submodules += fsm
fsm.act("IDLE",
load.eq(1),
self.parameters.ack.eq(1),
If(self.parameters.stb, NextState("ACTIVE"))
)
fsm.act("ACTIVE",
self.busy.eq(1),
self.source.stb.eq(1),
If(self.source.ack,
ce.eq(1),
If(last, NextState("IDLE"))
)
)
# Add buffers on Endpoints (can be used to improve timings)
class BufferizeEndpoints(ModuleTransformer):
def __init__(self, *names):
self.names = names
def transform_instance(self, submodule):
endpoints = get_endpoints(submodule)
sinks = {}
sources = {}
for name, endpoint in endpoints.items():
if not self.names or name in self.names:
if isinstance(endpoint, Sink):
sinks.update({name: endpoint})
elif isinstance(endpoint, Source):
sources.update({name: endpoint})
# add buffer on sinks
for name, sink in sinks.items():
buf = Buffer(sink.description)
submodule.submodules += buf
setattr(submodule, name, buf.d)
submodule.comb += Record.connect(buf.q, sink)
# add buffer on sources
for name, source in sources.items():
buf = Buffer(source.description)
submodule.submodules += buf
submodule.comb += Record.connect(source, buf.d)
setattr(submodule, name, buf.q)

365
migen/actorlib/packet.py
View file

@ -1,365 +0,0 @@
from migen.fhdl.std import *
from migen.genlib.roundrobin import *
from migen.genlib.record import *
from migen.flow.actor import *
from migen.actorlib.fifo import SyncFIFO
from migen.genlib.fsm import FSM, NextState
from migen.genlib.misc import reverse_bytes, Counter
class Status(Module):
def __init__(self, endpoint):
self.sop = sop = Signal()
self.eop = eop =Signal()
self.ongoing = Signal()
ongoing = Signal()
self.comb += \
If(endpoint.stb,
sop.eq(endpoint.sop),
eop.eq(endpoint.eop & endpoint.ack)
)
self.sync += ongoing.eq((sop | ongoing) & ~eop)
self.comb += self.ongoing.eq((sop | ongoing) & ~eop)
class Arbiter(Module):
def __init__(self, masters, slave):
if len(masters) == 0:
pass
elif len(masters) == 1:
self.grant = Signal()
self.comb += Record.connect(masters.pop(), slave)
else:
self.submodules.rr = RoundRobin(len(masters))
self.grant = self.rr.grant
cases = {}
for i, master in enumerate(masters):
status = Status(master)
self.submodules += status
self.comb += self.rr.request[i].eq(status.ongoing)
cases[i] = [Record.connect(master, slave)]
self.comb += Case(self.grant, cases)
class Dispatcher(Module):
def __init__(self, master, slaves, one_hot=False):
if len(slaves) == 0:
self.sel = Signal()
elif len(slaves) == 1:
self.comb += Record.connect(master, slaves.pop())
self.sel = Signal()
else:
if one_hot:
self.sel = Signal(len(slaves))
else:
self.sel = Signal(max=len(slaves))
# # #
status = Status(master)
self.submodules += status
sel = Signal.like(self.sel)
sel_ongoing = Signal.like(self.sel)
self.sync += \
If(status.sop,
sel_ongoing.eq(self.sel)
)
self.comb += \
If(status.sop,
sel.eq(self.sel)
).Else(
sel.eq(sel_ongoing)
)
cases = {}
for i, slave in enumerate(slaves):
if one_hot:
idx = 2**i
else:
idx = i
cases[idx] = [Record.connect(master, slave)]
cases["default"] = [master.ack.eq(1)]
self.comb += Case(sel, cases)
class HeaderField:
def __init__(self, byte, offset, width):
self.byte = byte
self.offset = offset
self.width = width
class Header:
def __init__(self, fields, length, swap_field_bytes=True):
self.fields = fields
self.length = length
self.swap_field_bytes = swap_field_bytes
def get_layout(self):
layout = []
for k, v in sorted(self.fields.items()):
layout.append((k, v.width))
return layout
def get_field(self, obj, name, width):
if "_lsb" in name:
field = getattr(obj, name.replace("_lsb", ""))[:width]
elif "_msb" in name:
field = getattr(obj, name.replace("_msb", ""))[width:2*width]
else:
field = getattr(obj, name)
return field
def encode(self, obj, signal):
r = []
for k, v in sorted(self.fields.items()):
start = v.byte*8+v.offset
end = start+v.width
field = self.get_field(obj, k, v.width)
if self.swap_field_bytes:
field = reverse_bytes(field)
r.append(signal[start:end].eq(field))
return r
def decode(self, signal, obj):
r = []
for k, v in sorted(self.fields.items()):
start = v.byte*8+v.offset
end = start+v.width
field = self.get_field(obj, k, v.width)
if self.swap_field_bytes:
r.append(field.eq(reverse_bytes(signal[start:end])))
else:
r.append(field.eq(signal[start:end]))
return r
class Packetizer(Module):
def __init__(self, sink_description, source_description, header):
self.sink = sink = Sink(sink_description)
self.source = source = Source(source_description)
self.header = Signal(header.length*8)
# # #
dw = flen(self.sink.data)
header_reg = Signal(header.length*8)
header_words = (header.length*8)//dw
load = Signal()
shift = Signal()
counter = Counter(max=max(header_words, 2))
self.submodules += counter
self.comb += header.encode(sink, self.header)
if header_words == 1:
self.sync += [
If(load,
header_reg.eq(self.header)
)
]
else:
self.sync += [
If(load,
header_reg.eq(self.header)
).Elif(shift,
header_reg.eq(Cat(header_reg[dw:], Signal(dw)))
)
]
fsm = FSM(reset_state="IDLE")
self.submodules += fsm
if header_words == 1:
idle_next_state = "COPY"
else:
idle_next_state = "SEND_HEADER"
fsm.act("IDLE",
sink.ack.eq(1),
counter.reset.eq(1),
If(sink.stb & sink.sop,
sink.ack.eq(0),
source.stb.eq(1),
source.sop.eq(1),
source.eop.eq(0),
source.data.eq(self.header[:dw]),
If(source.stb & source.ack,
load.eq(1),
NextState(idle_next_state)
)
)
)
if header_words != 1:
fsm.act("SEND_HEADER",
source.stb.eq(1),
source.sop.eq(0),
source.eop.eq(0),
source.data.eq(header_reg[dw:2*dw]),
If(source.stb & source.ack,
shift.eq(1),
counter.ce.eq(1),
If(counter.value == header_words-2,
NextState("COPY")
)
)
)
fsm.act("COPY",
source.stb.eq(sink.stb),
source.sop.eq(0),
source.eop.eq(sink.eop),
source.data.eq(sink.data),
source.error.eq(sink.error),
If(source.stb & source.ack,
sink.ack.eq(1),
If(source.eop,
NextState("IDLE")
)
)
)
class Depacketizer(Module):
def __init__(self, sink_description, source_description, header):
self.sink = sink = Sink(sink_description)
self.source = source = Source(source_description)
self.header = Signal(header.length*8)
# # #
dw = flen(sink.data)
header_words = (header.length*8)//dw
shift = Signal()
counter = Counter(max=max(header_words, 2))
self.submodules += counter
if header_words == 1:
self.sync += \
If(shift,
self.header.eq(sink.data)
)
else:
self.sync += \
If(shift,
self.header.eq(Cat(self.header[dw:], sink.data))
)
fsm = FSM(reset_state="IDLE")
self.submodules += fsm
if header_words == 1:
idle_next_state = "COPY"
else:
idle_next_state = "RECEIVE_HEADER"
fsm.act("IDLE",
sink.ack.eq(1),
counter.reset.eq(1),
If(sink.stb,
shift.eq(1),
NextState(idle_next_state)
)
)
if header_words != 1:
fsm.act("RECEIVE_HEADER",
sink.ack.eq(1),
If(sink.stb,
counter.ce.eq(1),
shift.eq(1),
If(counter.value == header_words-2,
NextState("COPY")
)
)
)
no_payload = Signal()
self.sync += \
If(fsm.before_entering("COPY"),
source.sop.eq(1),
no_payload.eq(sink.eop)
).Elif(source.stb & source.ack,
source.sop.eq(0)
)
if hasattr(sink, "error"):
self.comb += source.error.eq(sink.error)
self.comb += [
source.eop.eq(sink.eop | no_payload),
source.data.eq(sink.data),
header.decode(self.header, source)
]
fsm.act("COPY",
sink.ack.eq(source.ack),
source.stb.eq(sink.stb | no_payload),
If(source.stb & source.ack & source.eop,
NextState("IDLE")
)
)
class Buffer(Module):
def __init__(self, description, data_depth, cmd_depth=4, almost_full=None):
self.sink = sink = Sink(description)
self.source = source = Source(description)
# # #
sink_status = Status(self.sink)
source_status = Status(self.source)
self.submodules += sink_status, source_status
# store incoming packets
# cmds
def cmd_description():
layout = [("error", 1)]
return EndpointDescription(layout)
cmd_fifo = SyncFIFO(cmd_description(), cmd_depth)
self.submodules += cmd_fifo
self.comb += cmd_fifo.sink.stb.eq(sink_status.eop)
if hasattr(sink, "error"):
self.comb += cmd_fifo.sink.error.eq(sink.error)
# data
data_fifo = SyncFIFO(description, data_depth, buffered=True)
self.submodules += data_fifo
self.comb += [
Record.connect(self.sink, data_fifo.sink),
data_fifo.sink.stb.eq(self.sink.stb & cmd_fifo.sink.ack),
self.sink.ack.eq(data_fifo.sink.ack & cmd_fifo.sink.ack),
]
# output packets
self.fsm = fsm = FSM(reset_state="IDLE")
self.submodules += fsm
fsm.act("IDLE",
If(cmd_fifo.source.stb,
NextState("SEEK_SOP")
)
)
fsm.act("SEEK_SOP",
If(~data_fifo.source.sop,
data_fifo.source.ack.eq(1)
).Else(
NextState("OUTPUT")
)
)
if hasattr(source, "error"):
source_error = self.source.error
else:
source_error = Signal()
fsm.act("OUTPUT",
Record.connect(data_fifo.source, self.source),
source_error.eq(cmd_fifo.source.error),
If(source_status.eop,
cmd_fifo.source.ack.eq(1),
NextState("IDLE")
)
)
# compute almost full
if almost_full is not None:
self.almost_full = Signal()
self.comb += self.almost_full.eq(data_fifo.fifo.level > almost_full)

122
migen/actorlib/sim.py
View file

@ -1,122 +0,0 @@
from migen.fhdl.std import *
from migen.flow.actor import *
from migen.flow.transactions import *
from migen.util.misc import xdir
def _sim_multiread(sim, obj):
if isinstance(obj, Signal):
return sim.rd(obj)
else:
r = {}
for k, v in xdir(obj, True):
rd = _sim_multiread(sim, v)
if isinstance(rd, int) or rd:
r[k] = rd
return r
def _sim_multiwrite(sim, obj, value):
if isinstance(obj, Signal):
sim.wr(obj, value)
else:
for k, v in value.items():
_sim_multiwrite(sim, getattr(obj, k), v)
# Generators yield None or a tuple of Tokens.
# Tokens for Sink endpoints are pulled and the "value" field filled in.
# Tokens for Source endpoints are pushed according to their "value" field.
#
# NB: the possibility to push several tokens at once is important to interact
# with actors that only accept a group of tokens when all of them are available.
class TokenExchanger(Module):
def __init__(self, generator, actor):
self.generator = generator
self.actor = actor
self.active = set()
self.busy = True
self.done = False
def _process_transactions(self, selfp):
completed = set()
for token in self.active:
ep = getattr(self.actor, token.endpoint)
if isinstance(ep, Sink):
if selfp.simulator.rd(ep.ack) and selfp.simulator.rd(ep.stb):
token.value = _sim_multiread(selfp.simulator, ep.payload)
completed.add(token)
selfp.simulator.wr(ep.ack, 0)
elif isinstance(ep, Source):
if selfp.simulator.rd(ep.ack) and selfp.simulator.rd(ep.stb):
completed.add(token)
selfp.simulator.wr(ep.stb, 0)
else:
raise TypeError
self.active -= completed
if not self.active:
self.busy = True
def _update_control_signals(self, selfp):
for token in self.active:
ep = getattr(self.actor, token.endpoint)
if isinstance(ep, Sink):
selfp.simulator.wr(ep.ack, 1)
elif isinstance(ep, Source):
_sim_multiwrite(selfp.simulator, ep.payload, token.value)
selfp.simulator.wr(ep.stb, 1)
else:
raise TypeError
def _next_transactions(self):
try:
transactions = next(self.generator)
except StopIteration:
self.busy = False
self.done = True
raise StopSimulation
if isinstance(transactions, Token):
self.active = {transactions}
elif isinstance(transactions, (tuple, list, set)):
self.active = set(transactions)
elif transactions is None:
self.active = set()
else:
raise TypeError
if self.active and all(transaction.idle_wait for transaction in self.active):
self.busy = False
def do_simulation(self, selfp):
if self.active:
self._process_transactions(selfp)
if not self.active:
self._next_transactions()
self._update_control_signals(selfp)
do_simulation.passive = True
class SimActor(Module):
def __init__(self, generator):
self.busy = Signal()
self.submodules.token_exchanger = TokenExchanger(generator, self)
def do_simulation(self, selfp):
selfp.busy = self.token_exchanger.busy
do_simulation.passive = True
def _dumper_gen(prefix):
while True:
t = Token("result")
yield t
if len(t.value) > 1:
s = str(t.value)
else:
s = str(list(t.value.values())[0])
print(prefix + s)
class Dumper(SimActor):
def __init__(self, layout, prefix=""):
self.result = Sink(layout)
SimActor.__init__(self, _dumper_gen(prefix))

184
migen/actorlib/spi.py
View file

@ -1,184 +0,0 @@
# Simple Processor Interface
from migen.fhdl.std import *
from migen.bank.description import *
from migen.flow.actor import *
from migen.flow.network import *
from migen.flow import plumbing
from migen.actorlib import misc
# layout is a list of tuples, either:
# - (name, nbits, [reset value], [alignment bits])
# - (name, sublayout)
def _convert_layout(layout):
r = []
for element in layout:
if isinstance(element[1], list):
r.append((element[0], _convert_layout(element[1])))
else:
r.append((element[0], element[1]))
return r
(MODE_EXTERNAL, MODE_SINGLE_SHOT, MODE_CONTINUOUS) = range(3)
class SingleGenerator(Module, AutoCSR):
def __init__(self, layout, mode):
self.source = Source(_convert_layout(layout))
self.busy = Signal()
self.comb += self.busy.eq(self.source.stb)
if mode == MODE_EXTERNAL:
self.trigger = Signal()
trigger = self.trigger
elif mode == MODE_SINGLE_SHOT:
self._shoot = CSR()
trigger = self._shoot.re
elif mode == MODE_CONTINUOUS:
self._enable = CSRStorage()
trigger = self._enable.storage
else:
raise ValueError
self.sync += If(self.source.ack | ~self.source.stb, self.source.stb.eq(trigger))
self._create_csrs(layout, self.source.payload, mode != MODE_SINGLE_SHOT)
def _create_csrs(self, layout, target, atomic, prefix=""):
for element in layout:
if isinstance(element[1], list):
self._create_csrs(element[1], atomic,
getattr(target, element[0]),
element[0] + "_")
else:
name = element[0]
nbits = element[1]
if len(element) > 2:
reset = element[2]
else:
reset = 0
if len(element) > 3:
alignment = element[3]
else:
alignment = 0
regname = prefix + name
reg = CSRStorage(nbits + alignment, reset=reset, atomic_write=atomic,
alignment_bits=alignment, name=regname)
setattr(self, "_"+regname, reg)
self.sync += If(self.source.ack | ~self.source.stb,
getattr(target, name).eq(reg.storage))
class Collector(Module, AutoCSR):
def __init__(self, layout, depth=1024):
self.sink = Sink(layout)
self.busy = Signal()
dw = sum(len(s) for s in self.sink.payload.flatten())
self._wa = CSRStorage(bits_for(depth-1), write_from_dev=True)
self._wc = CSRStorage(bits_for(depth), write_from_dev=True, atomic_write=True)
self._ra = CSRStorage(bits_for(depth-1))
self._rd = CSRStatus(dw)
###
mem = Memory(dw, depth)
self.specials += mem
wp = mem.get_port(write_capable=True)
rp = mem.get_port()
self.specials += wp, rp
self.comb += [
self.busy.eq(0),
If(self._wc.r != 0,
self.sink.ack.eq(1),
If(self.sink.stb,
self._wa.we.eq(1),
self._wc.we.eq(1),
wp.we.eq(1)
)
),
self._wa.dat_w.eq(self._wa.storage + 1),
self._wc.dat_w.eq(self._wc.storage - 1),
wp.adr.eq(self._wa.storage),
wp.dat_w.eq(self.sink.payload.raw_bits()),
rp.adr.eq(self._ra.storage),
self._rd.status.eq(rp.dat_r)
]
class _DMAController(Module):
def __init__(self, bus_accessor, bus_aw, bus_dw, mode, base_reset=0, length_reset=0):
self.alignment_bits = bits_for(bus_dw//8) - 1
layout = [
("length", bus_aw + self.alignment_bits, length_reset, self.alignment_bits),
("base", bus_aw + self.alignment_bits, base_reset, self.alignment_bits)
]
self.generator = SingleGenerator(layout, mode)
self._busy = CSRStatus()
self.length = self.generator._length.storage
self.base = self.generator._base.storage
if hasattr(self.generator, "trigger"):
self.trigger = self.generator.trigger
def get_csrs(self):
return self.generator.get_csrs() + [self._busy]
class DMAReadController(_DMAController):
def __init__(self, bus_accessor, *args, **kwargs):
bus_aw = flen(bus_accessor.address.a)
bus_dw = flen(bus_accessor.data.d)
_DMAController.__init__(self, bus_accessor, bus_aw, bus_dw, *args, **kwargs)
g = DataFlowGraph()
g.add_pipeline(self.generator,
misc.IntSequence(bus_aw, bus_aw),
AbstractActor(plumbing.Buffer),
bus_accessor,
AbstractActor(plumbing.Buffer))
comp_actor = CompositeActor(g)
self.submodules += comp_actor
self.data = comp_actor.q
self.busy = comp_actor.busy
self.comb += self._busy.status.eq(self.busy)
class DMAWriteController(_DMAController):
def __init__(self, bus_accessor, *args, ack_when_inactive=False, **kwargs):
bus_aw = flen(bus_accessor.address_data.a)
bus_dw = flen(bus_accessor.address_data.d)
_DMAController.__init__(self, bus_accessor, bus_aw, bus_dw, *args, **kwargs)
g = DataFlowGraph()
adr_buffer = AbstractActor(plumbing.Buffer)
int_sequence = misc.IntSequence(bus_aw, bus_aw)
g.add_pipeline(self.generator,
int_sequence,
adr_buffer)
g.add_connection(adr_buffer, bus_accessor, sink_subr=["a"])
g.add_connection(AbstractActor(plumbing.Buffer), bus_accessor, sink_subr=["d"])
comp_actor = CompositeActor(g)
self.submodules += comp_actor
if ack_when_inactive:
demultiplexer = plumbing.Demultiplexer([("d", bus_dw)], 2)
self.comb += [
demultiplexer.sel.eq(~adr_buffer.busy),
demultiplexer.source0.connect(comp_actor.d),
demultiplexer.source1.ack.eq(1),
]
self.submodules += demultiplexer
self.data = demultiplexer.sink
else:
self.data = comp_actor.d
self.busy = comp_actor.busy
self.comb += self._busy.status.eq(self.busy)

269
migen/actorlib/structuring.py
View file

@ -1,269 +0,0 @@
from copy import copy
from migen.fhdl.std import *
from migen.genlib.record import *
from migen.flow.actor import *
def _rawbits_layout(l):
if isinstance(l, int):
return [("rawbits", l)]
else:
return l
class Cast(CombinatorialActor):
def __init__(self, layout_from, layout_to, reverse_from=False, reverse_to=False):
self.sink = Sink(_rawbits_layout(layout_from))
self.source = Source(_rawbits_layout(layout_to))
CombinatorialActor.__init__(self)
###
sigs_from = self.sink.payload.flatten()
if reverse_from:
sigs_from = list(reversed(sigs_from))
sigs_to = self.source.payload.flatten()
if reverse_to:
sigs_to = list(reversed(sigs_to))
if sum(flen(s) for s in sigs_from) != sum(flen(s) for s in sigs_to):
raise TypeError
self.comb += Cat(*sigs_to).eq(Cat(*sigs_from))
def pack_layout(l, n):
return [("chunk"+str(i), l) for i in range(n)]
class Unpack(Module):
def __init__(self, n, layout_to, reverse=False):
self.source = source = Source(layout_to)
description_from = copy(source.description)
description_from.payload_layout = pack_layout(description_from.payload_layout, n)
self.sink = sink = Sink(description_from)
self.busy = Signal()
###
mux = Signal(max=n)
first = Signal()
last = Signal()
self.comb += [
first.eq(mux == 0),
last.eq(mux == (n-1)),
source.stb.eq(sink.stb),
sink.ack.eq(last & source.ack)
]
self.sync += [
If(source.stb & source.ack,
If(last,
mux.eq(0)
).Else(
mux.eq(mux + 1)
)
)
]
cases = {}
for i in range(n):
chunk = n-i-1 if reverse else i
cases[i] = [source.payload.raw_bits().eq(getattr(sink.payload, "chunk"+str(chunk)).raw_bits())]
self.comb += Case(mux, cases).makedefault()
for f in description_from.param_layout:
src = getattr(self.sink, f[0])
dst = getattr(self.source, f[0])
self.comb += dst.eq(src)
if description_from.packetized:
self.comb += [
source.sop.eq(sink.sop & first),
source.eop.eq(sink.eop & last)
]
class Pack(Module):
def __init__(self, layout_from, n, reverse=False):
self.sink = sink = Sink(layout_from)
description_to = copy(sink.description)
description_to.payload_layout = pack_layout(description_to.payload_layout, n)
self.source = source = Source(description_to)
self.busy = Signal()
###
demux = Signal(max=n)
load_part = Signal()
strobe_all = Signal()
cases = {}
for i in range(n):
chunk = n-i-1 if reverse else i
cases[i] = [getattr(source.payload, "chunk"+str(chunk)).raw_bits().eq(sink.payload.raw_bits())]
self.comb += [
self.busy.eq(strobe_all),
sink.ack.eq(~strobe_all | source.ack),
source.stb.eq(strobe_all),
load_part.eq(sink.stb & sink.ack)
]
for f in description_to.param_layout:
src = getattr(self.sink, f[0])
dst = getattr(self.source, f[0])
self.sync += If(load_part, dst.eq(src))
if description_to.packetized:
demux_last = ((demux == (n - 1)) | sink.eop)
else:
demux_last = (demux == (n - 1))
self.sync += [
If(source.ack, strobe_all.eq(0)),
If(load_part,
Case(demux, cases),
If(demux_last,
demux.eq(0),
strobe_all.eq(1)
).Else(
demux.eq(demux + 1)
)
)
]
if description_to.packetized:
self.sync += [
If(source.stb & source.ack,
source.sop.eq(sink.sop),
source.eop.eq(sink.eop),
).Elif(sink.stb & sink.ack,
source.sop.eq(sink.sop | source.sop),
source.eop.eq(sink.eop | source.eop)
)
]
class Chunkerize(CombinatorialActor):
def __init__(self, layout_from, layout_to, n, reverse=False):
self.sink = Sink(layout_from)
if isinstance(layout_to, EndpointDescription):
layout_to = copy(layout_to)
layout_to.payload_layout = pack_layout(layout_to.payload_layout, n)
else:
layout_to = pack_layout(layout_to, n)
self.source = Source(layout_to)
CombinatorialActor.__init__(self)
###
for i in range(n):
chunk = n-i-1 if reverse else i
for f in self.sink.description.payload_layout:
src = getattr(self.sink, f[0])
dst = getattr(getattr(self.source, "chunk"+str(chunk)), f[0])
self.comb += dst.eq(src[i*flen(src)//n:(i+1)*flen(src)//n])
for f in self.sink.description.param_layout:
src = getattr(self.sink, f[0])
dst = getattr(self.source, f[0])
self.comb += dst.eq(src)
class Unchunkerize(CombinatorialActor):
def __init__(self, layout_from, n, layout_to, reverse=False):
if isinstance(layout_from, EndpointDescription):
fields = layout_from.payload_layout
layout_from = copy(layout_from)
layout_from.payload_layout = pack_layout(layout_from.payload_layout, n)
else:
fields = layout_from
layout_from = pack_layout(layout_from, n)
self.sink = Sink(layout_from)
self.source = Source(layout_to)
CombinatorialActor.__init__(self)
###
for i in range(n):
chunk = n-i-1 if reverse else i
for f in fields:
src = getattr(getattr(self.sink, "chunk"+str(chunk)), f[0])
dst = getattr(self.source, f[0])
self.comb += dst[i*flen(dst)//n:(i+1)*flen(dst)//n].eq(src)
for f in self.sink.description.param_layout:
src = getattr(self.sink, f[0])
dst = getattr(self.source, f[0])
self.comb += dst.eq(src)
class Converter(Module):
def __init__(self, layout_from, layout_to, reverse=False):
self.sink = Sink(layout_from)
self.source = Source(layout_to)
self.busy = Signal()
###
width_from = flen(self.sink.payload.raw_bits())
width_to = flen(self.source.payload.raw_bits())
# downconverter
if width_from > width_to:
if width_from % width_to:
raise ValueError
ratio = width_from//width_to
self.submodules.chunkerize = Chunkerize(layout_from, layout_to, ratio, reverse)
self.submodules.unpack = Unpack(ratio, layout_to)
self.comb += [
Record.connect(self.sink, self.chunkerize.sink),
Record.connect(self.chunkerize.source, self.unpack.sink),
Record.connect(self.unpack.source, self.source),
self.busy.eq(self.unpack.busy)
]
# upconverter
elif width_to > width_from:
if width_to % width_from:
raise ValueError
ratio = width_to//width_from
self.submodules.pack = Pack(layout_from, ratio)
self.submodules.unchunkerize = Unchunkerize(layout_from, ratio, layout_to, reverse)
self.comb += [
Record.connect(self.sink, self.pack.sink),
Record.connect(self.pack.source, self.unchunkerize.sink),
Record.connect(self.unchunkerize.source, self.source),
self.busy.eq(self.pack.busy)
]
# direct connection
else:
self.comb += Record.connect(self.sink, self.source)
class Pipeline(Module):
def __init__(self, *modules):
self.busy = Signal()
n = len(modules)
m = modules[0]
# expose sink of first module
# if available
if hasattr(m, "sink"):
self.sink = m.sink
if hasattr(m, "busy"):
busy = m.busy
else:
busy = 0
for i in range(1, n):
m_n = modules[i]
if hasattr(m_n, "busy"):
busy_n = m_n.busy
else:
busy_n = 0
self.comb += m.source.connect(m_n.sink)
m = m_n
busy = busy | busy_n
# expose source of last module
# if available
if hasattr(m, "source"):
self.source = m.source
self.comb += self.busy.eq(busy)

0
migen/bank/__init__.py
View file

25
migen/bank/bank.py
View file

@ -1,25 +0,0 @@
from migen.fhdl.std import Module, bits_for
from migen.bank.description import CSR
class GenericBank(Module):
def __init__(self, description, busword):
# Turn description into simple CSRs and claim ownership of compound CSR modules
self.simple_csrs = []
for c in description:
if isinstance(c, CSR):
self.simple_csrs.append(c)
else:
c.finalize(busword)
self.simple_csrs += c.get_simple_csrs()
self.submodules += c
self.decode_bits = bits_for(len(self.simple_csrs)-1)
def get_offset(description, name, busword):
offset = 0
for c in description:
if c.name == name:
return offset
offset += (c.size + busword - 1)//busword
raise KeyError("CSR not found: "+name)

82
migen/bank/csrgen.py
View file

@ -1,82 +0,0 @@
from migen.util.misc import xdir
from migen.fhdl.std import *
from migen.bus import csr
from migen.bank.bank import GenericBank
class Bank(GenericBank):
def __init__(self, description, address=0, bus=None):
if bus is None:
bus = csr.Interface()
self.bus = bus
###
GenericBank.__init__(self, description, flen(self.bus.dat_w))
sel = Signal()
self.comb += sel.eq(self.bus.adr[9:] == address)
for i, c in enumerate(self.simple_csrs):
self.comb += [
c.r.eq(self.bus.dat_w[:c.size]),
c.re.eq(sel & \
self.bus.we & \
(self.bus.adr[:self.decode_bits] == i))
]
brcases = dict((i, self.bus.dat_r.eq(c.w)) for i, c in enumerate(self.simple_csrs))
self.sync += [
self.bus.dat_r.eq(0),
If(sel, Case(self.bus.adr[:self.decode_bits], brcases))
]
# address_map(name, memory) returns the CSR offset at which to map
# the CSR object (register bank or memory).
# If memory=None, the object is the register bank of object source.name.
# Otherwise, it is a memory object belonging to source.name.
# address_map is called exactly once for each object at each call to
# scan(), so it can have side effects.
class BankArray(Module):
def __init__(self, source, address_map, *ifargs, **ifkwargs):
self.source = source
self.address_map = address_map
self.scan(ifargs, ifkwargs)
def scan(self, ifargs, ifkwargs):
self.banks = []
self.srams = []
for name, obj in xdir(self.source, True):
if hasattr(obj, "get_csrs"):
csrs = obj.get_csrs()
else:
csrs = []
if hasattr(obj, "get_memories"):
memories = obj.get_memories()
for memory in memories:
mapaddr = self.address_map(name, memory)
if mapaddr is None:
continue
sram_bus = csr.Interface(*ifargs, **ifkwargs)
mmap = csr.SRAM(memory, mapaddr, bus=sram_bus)
self.submodules += mmap
csrs += mmap.get_csrs()
self.srams.append((name, memory, mapaddr, mmap))
if csrs:
mapaddr = self.address_map(name, None)
if mapaddr is None:
continue
bank_bus = csr.Interface(*ifargs, **ifkwargs)
rmap = Bank(csrs, mapaddr, bus=bank_bus)
self.submodules += rmap
self.banks.append((name, csrs, mapaddr, rmap))
def get_rmaps(self):
return [rmap for name, csrs, mapaddr, rmap in self.banks]
def get_mmaps(self):
return [mmap for name, memory, mapaddr, mmap in self.srams]
def get_buses(self):
return [i.bus for i in self.get_rmaps() + self.get_mmaps()]

133
migen/bank/description.py
View file

@ -1,133 +0,0 @@
from migen.util.misc import xdir
from migen.fhdl.std import *
from migen.fhdl.tracer import get_obj_var_name
class _CSRBase(HUID):
def __init__(self, size, name):
HUID.__init__(self)
self.name = get_obj_var_name(name)
if self.name is None:
raise ValueError("Cannot extract CSR name from code, need to specify.")
self.size = size
class CSR(_CSRBase):
def __init__(self, size=1, name=None):
_CSRBase.__init__(self, size, name)
self.re = Signal(name=self.name + "_re")
self.r = Signal(self.size, name=self.name + "_r")
self.w = Signal(self.size, name=self.name + "_w")
class _CompoundCSR(_CSRBase, Module):
def __init__(self, size, name):
_CSRBase.__init__(self, size, name)
self.simple_csrs = []
def get_simple_csrs(self):
if not self.finalized:
raise FinalizeError
return self.simple_csrs
def do_finalize(self, busword):
raise NotImplementedError
class CSRStatus(_CompoundCSR):
def __init__(self, size=1, reset=0, name=None):
_CompoundCSR.__init__(self, size, name)
self.status = Signal(self.size, reset=reset)
def do_finalize(self, busword):
nwords = (self.size + busword - 1)//busword
for i in reversed(range(nwords)):
nbits = min(self.size - i*busword, busword)
sc = CSR(nbits, self.name + str(i) if nwords > 1 else self.name)
self.comb += sc.w.eq(self.status[i*busword:i*busword+nbits])
self.simple_csrs.append(sc)
class CSRStorage(_CompoundCSR):
def __init__(self, size=1, reset=0, atomic_write=False, write_from_dev=False, alignment_bits=0, name=None):
_CompoundCSR.__init__(self, size, name)
self.alignment_bits = alignment_bits
self.storage_full = Signal(self.size, reset=reset)
self.storage = Signal(self.size - self.alignment_bits, reset=reset >> alignment_bits)
self.comb += self.storage.eq(self.storage_full[self.alignment_bits:])
self.atomic_write = atomic_write
self.re = Signal()
if write_from_dev:
self.we = Signal()
self.dat_w = Signal(self.size - self.alignment_bits)
self.sync += If(self.we, self.storage_full.eq(self.dat_w << self.alignment_bits))
def do_finalize(self, busword):
nwords = (self.size + busword - 1)//busword
if nwords > 1 and self.atomic_write:
backstore = Signal(self.size - busword, name=self.name + "_backstore")
for i in reversed(range(nwords)):
nbits = min(self.size - i*busword, busword)
sc = CSR(nbits, self.name + str(i) if nwords else self.name)
self.simple_csrs.append(sc)
lo = i*busword
hi = lo+nbits
# read
if lo >= self.alignment_bits:
self.comb += sc.w.eq(self.storage_full[lo:hi])
elif hi > self.alignment_bits:
self.comb += sc.w.eq(Cat(Replicate(0, hi - self.alignment_bits),
self.storage_full[self.alignment_bits:hi]))
else:
self.comb += sc.w.eq(0)
# write
if nwords > 1 and self.atomic_write:
if i:
self.sync += If(sc.re, backstore[lo-busword:hi-busword].eq(sc.r))
else:
self.sync += If(sc.re, self.storage_full.eq(Cat(sc.r, backstore)))
else:
self.sync += If(sc.re, self.storage_full[lo:hi].eq(sc.r))
self.sync += self.re.eq(sc.re)
def csrprefix(prefix, csrs, done):
for csr in csrs:
if csr.huid not in done:
csr.name = prefix + csr.name
done.add(csr.huid)
def memprefix(prefix, memories, done):
for memory in memories:
if memory.huid not in done:
memory.name_override = prefix + memory.name_override
done.add(memory.huid)
def _make_gatherer(method, cls, prefix_cb):
def gatherer(self):
try:
exclude = self.autocsr_exclude
except AttributeError:
exclude = {}
try:
prefixed = self.__prefixed
except AttributeError:
prefixed = self.__prefixed = set()
r = []
for k, v in xdir(self, True):
if k not in exclude:
if isinstance(v, cls):
r.append(v)
elif hasattr(v, method) and callable(getattr(v, method)):
items = getattr(v, method)()
prefix_cb(k + "_", items, prefixed)
r += items
return sorted(r, key=lambda x: x.huid)
return gatherer
class AutoCSR:
get_memories = _make_gatherer("get_memories", Memory, memprefix)
get_csrs = _make_gatherer("get_csrs", _CSRBase, csrprefix)

83
migen/bank/eventmanager.py
View file

@ -1,83 +0,0 @@
from migen.util.misc import xdir
from migen.fhdl.std import *
from migen.bank.description import *
from migen.genlib.misc import optree
class _EventSource(HUID):
def __init__(self):
HUID.__init__(self)
self.status = Signal() # value in the status register
self.pending = Signal() # value in the pending register + assert irq if unmasked
self.trigger = Signal() # trigger signal interface to the user design
self.clear = Signal() # clearing attempt by W1C to pending register, ignored by some event sources
# set on a positive trigger pulse
class EventSourcePulse(Module, _EventSource):
def __init__(self):
_EventSource.__init__(self)
self.comb += self.status.eq(0)
self.sync += [
If(self.clear, self.pending.eq(0)),
If(self.trigger, self.pending.eq(1))
]
# set on the falling edge of the trigger, status = trigger
class EventSourceProcess(Module, _EventSource):
def __init__(self):
_EventSource.__init__(self)
self.comb += self.status.eq(self.trigger)
old_trigger = Signal()
self.sync += [
If(self.clear, self.pending.eq(0)),
old_trigger.eq(self.trigger),
If(~self.trigger & old_trigger, self.pending.eq(1))
]
# all status set by external trigger
class EventSourceLevel(Module, _EventSource):
def __init__(self):
_EventSource.__init__(self)
self.comb += [
self.status.eq(self.trigger),
self.pending.eq(self.trigger)
]
class EventManager(Module, AutoCSR):
def __init__(self):
self.irq = Signal()
def do_finalize(self):
sources_u = [v for k, v in xdir(self, True) if isinstance(v, _EventSource)]
sources = sorted(sources_u, key=lambda x: x.huid)
n = len(sources)
self.status = CSR(n)
self.pending = CSR(n)
self.enable = CSRStorage(n)
for i, source in enumerate(sources):
self.comb += [
self.status.w[i].eq(source.status),
If(self.pending.re & self.pending.r[i], source.clear.eq(1)),
self.pending.w[i].eq(source.pending)
]
irqs = [self.pending.w[i] & self.enable.storage[i] for i in range(n)]
self.comb += self.irq.eq(optree("|", irqs))
def __setattr__(self, name, value):
object.__setattr__(self, name, value)
if isinstance(value, _EventSource):
if self.finalized:
raise FinalizeError
self.submodules += value
class SharedIRQ(Module):
def __init__(self, *event_managers):
self.irq = Signal()
self.comb += self.irq.eq(optree("|", [ev.irq for ev in event_managers]))

27
migen/bank/wbgen.py
View file

@ -1,27 +0,0 @@
from migen.fhdl.std import *
from migen.bus import wishbone
from migen.bank.bank import GenericBank
class Bank(GenericBank):
def __init__(self, description, bus=None):
if bus is None:
bus = wishbone.Interface()
self.bus = bus
###
GenericBank.__init__(self, description, flen(self.bus.dat_w))
for i, c in enumerate(self.simple_csrs):
self.comb += [
c.r.eq(self.bus.dat_w[:c.size]),
c.re.eq(self.bus.cyc & self.bus.stb & ~self.bus.ack & self.bus.we & \
(self.bus.adr[:self.decode_bits] == i))
]
brcases = dict((i, self.bus.dat_r.eq(c.w)) for i, c in enumerate(self.simple_csrs))
self.sync += [
Case(self.bus.adr[:self.decode_bits], brcases),
If(bus.ack, bus.ack.eq(0)).Elif(bus.cyc & bus.stb, bus.ack.eq(1))
]

0
mibuild/__init__.py → migen/build/__init__.py
View file

2
migen/build/altera/__init__.py Normal file
View file

@ -0,0 +1,2 @@
from migen.build.altera.platform import AlteraPlatform
from migen.build.altera.programmer import USBBlaster

3
mibuild/altera/common.py → migen/build/altera/common.py
View file

@ -1,4 +1,5 @@
from migen.fhdl.std import Instance, Module
from migen.fhdl.module import Module
from migen.fhdl.specials import Instance
from migen.genlib.io import DifferentialInput, DifferentialOutput

4
mibuild/altera/platform.py → migen/build/altera/platform.py
View file

@ -1,5 +1,5 @@
from mibuild.generic_platform import GenericPlatform
from mibuild.altera import common, quartus
from migen.build.generic_platform import GenericPlatform
from migen.build.altera import common, quartus
class AlteraPlatform(GenericPlatform):

2
mibuild/altera/programmer.py → migen/build/altera/programmer.py
View file

@ -1,6 +1,6 @@
import subprocess
from mibuild.generic_programmer import GenericProgrammer
from migen.build.generic_programmer import GenericProgrammer
class USBBlaster(GenericProgrammer):

12
mibuild/altera/quartus.py → migen/build/altera/quartus.py
View file

@ -5,9 +5,9 @@ import os
import subprocess
from migen.fhdl.structure import _Fragment
from mibuild.generic_platform import (Pins, IOStandard, Misc)
from mibuild import tools
from migen.build.generic_platform import Pins, IOStandard, Misc
from migen.build import tools
def _format_constraint(c, signame, fmt_r):
@ -92,7 +92,9 @@ def _build_files(device, sources, vincpaths, named_sc, named_pc, build_name):
def _run_quartus(build_name, quartus_path):
build_script_contents = """# Autogenerated by mibuild
build_script_contents = """# Autogenerated by Migen
set -e
quartus_map --read_settings_files=on --write_settings_files=off {build_name} -c {build_name}
quartus_fit --read_settings_files=off --write_settings_files=off {build_name} -c {build_name}
@ -111,7 +113,7 @@ quartus_sta {build_name} -c {build_name}
class AlteraQuartusToolchain:
def build(self, platform, fragment, build_dir="build", build_name="top",
quartus_path="/opt/Altera", run=True):
toolchain_path="/opt/Altera", run=True):
tools.mkdir_noerror(build_dir)
os.chdir(build_dir)
@ -131,7 +133,7 @@ class AlteraQuartusToolchain:
named_pc,
build_name)
if run:
_run_quartus(build_name, quartus_path)
_run_quartus(build_name, toolchain_path)
os.chdir("..")

4
mibuild/fpgalink_programmer.py → migen/build/fpgalink_programmer.py
View file

@ -1,7 +1,7 @@
import os
from mibuild.generic_programmer import GenericProgrammer
from mibuild.xilinx.programmer import _create_xsvf
from migen.build.generic_programmer import GenericProgrammer
from migen.build.xilinx.programmer import _create_xsvf
try:
import fl

32
mibuild/generic_platform.py → migen/build/generic_platform.py
View file

@ -1,13 +1,10 @@
import os
import sys
from migen.fhdl.std import Signal
from migen.fhdl.structure import Signal
from migen.genlib.record import Record
from migen.genlib.io import CRG
from migen.fhdl import verilog, edif
from migen.util.misc import autotype
from mibuild import tools
from migen.build import tools
class ConstraintError(Exception):
@ -283,17 +280,13 @@ class GenericPlatform:
def add_source(self, filename, language=None, library=None):
if language is None:
language = tools.language_by_filename(filename)
if language is None:
language = "verilog" # default to Verilog
language = "verilog"
if library is None:
library = "work" # default to work
library = "work"
filename = os.path.abspath(filename)
if sys.platform == "win32" or sys.platform == "cygwin":
filename = filename.replace("\\", "/")
self.sources.add((filename, language, library))
self.sources.add((os.path.abspath(filename), language, library))
def add_sources(self, path, *filenames, language=None, library=None):
for f in filenames:
@ -315,10 +308,7 @@ class GenericPlatform:
self.add_source(filename, language, library)
def add_verilog_include_path(self, path):
path = os.path.abspath(path)
if sys.platform == "win32" or sys.platform == "cygwin":
path = path.replace("\\", "/")
self.verilog_include_paths.add(path)
self.verilog_include_paths.add(os.path.abspath(path))
def resolve_signals(self, vns):
# resolve signal names in constraints
@ -349,15 +339,5 @@ class GenericPlatform:
def build(self, fragment):
raise NotImplementedError("GenericPlatform.build must be overloaded")
def build_cmdline(self, *args, **kwargs):
arg = sys.argv[1:]
if len(arg) % 2:
print("Missing value for option: {}".format(sys.argv[-1]))
sys.exit(1)
argdict = dict((k, autotype(v)) for k, v in zip(*[iter(arg)] * 2))
kwargs.update(argdict)
self.build(*args, **kwargs)
def create_programmer(self):
raise NotImplementedError

0
mibuild/generic_programmer.py → migen/build/generic_programmer.py
View file

2
migen/build/lattice/__init__.py Normal file
View file

@ -0,0 +1,2 @@
from migen.build.lattice.platform import LatticePlatform
from migen.build.lattice.programmer import LatticeProgrammer

8
mibuild/lattice/common.py → migen/build/lattice/common.py
View file

@ -1,6 +1,6 @@
from migen.fhdl.std import *
from migen.fhdl.module import Module
from migen.fhdl.specials import Instance
from migen.genlib.io import *
from migen.genlib.resetsync import AsyncResetSynchronizer
@ -36,6 +36,6 @@ class LatticeDDROutput:
return LatticeDDROutputImpl(dr.i1, dr.i2, dr.o, dr.clk)
lattice_special_overrides = {
AsyncResetSynchronizer: LatticeAsyncResetSynchronizer,
DDROutput: LatticeDDROutput
AsyncResetSynchronizer: LatticeAsyncResetSynchronizer,
DDROutput: LatticeDDROutput
}

13
mibuild/lattice/diamond.py → migen/build/lattice/diamond.py
View file

@ -2,14 +2,15 @@
# License: BSD
import os
import sys
import subprocess
import shutil
from migen.fhdl.structure import _Fragment
from mibuild.generic_platform import *
from mibuild import tools
from mibuild.lattice import common
from migen.build.generic_platform import *
from migen.build import tools
from migen.build.lattice import common
def _format_constraint(c):
@ -60,7 +61,7 @@ def _build_files(device, sources, vincpaths, build_name):
def _run_diamond(build_name, source, ver=None):
if sys.platform == "win32" or sys.platform == "cygwin":
build_script_contents = "REM Autogenerated by mibuild\n"
build_script_contents = "REM Autogenerated by Migen\n"
build_script_contents = "pnmainc " + build_name + ".tcl\n"
build_script_file = "build_" + build_name + ".bat"
tools.write_to_file(build_script_file, build_script_contents)
@ -75,7 +76,7 @@ def _run_diamond(build_name, source, ver=None):
class LatticeDiamondToolchain:
def build(self, platform, fragment, build_dir="build", build_name="top",
diamond_path="/opt/Diamond", run=True):
toolchain_path="/opt/Diamond", run=True):
tools.mkdir_noerror(build_dir)
os.chdir(build_dir)
@ -93,7 +94,7 @@ class LatticeDiamondToolchain:
tools.write_to_file(build_name + ".lpf", _build_lpf(named_sc, named_pc))
if run:
_run_diamond(build_name, diamond_path)
_run_diamond(build_name, toolchain_path)
os.chdir("..")

4
mibuild/lattice/platform.py → migen/build/lattice/platform.py
View file

@ -1,5 +1,5 @@
from mibuild.generic_platform import GenericPlatform
from mibuild.lattice import common, diamond
from migen.build.generic_platform import GenericPlatform
from migen.build.lattice import common, diamond
class LatticePlatform(GenericPlatform):

5
mibuild/lattice/programmer.py → migen/build/lattice/programmer.py
View file

@ -1,8 +1,9 @@
import os
import subprocess
from mibuild.generic_programmer import GenericProgrammer
from mibuild import tools
from migen.build.generic_programmer import GenericProgrammer
from migen.build import tools
# XXX Lattice programmer need an .xcf file, will need clean up and support for more parameters
_xcf_template = """

2
mibuild/openocd.py → migen/build/openocd.py
View file

@ -1,6 +1,6 @@
import subprocess
from mibuild.generic_programmer import GenericProgrammer
from migen.build.generic_programmer import GenericProgrammer
class OpenOCD(GenericProgrammer):

0
mibuild/platforms/__init__.py → migen/build/platforms/__init__.py
View file

5
mibuild/platforms/apf27.py → migen/build/platforms/apf27.py
View file

@ -1,5 +1,6 @@
from mibuild.generic_platform import *
from mibuild.xilinx import XilinxPlatform
from migen.build.generic_platform import *
from migen.build.xilinx import XilinxPlatform
_ios = [
("clk0", 0, Pins("N9"), IOStandard("LVCMOS18")),

5
mibuild/platforms/apf51.py → migen/build/platforms/apf51.py
View file

@ -1,5 +1,6 @@
from mibuild.generic_platform import *
from mibuild.xilinx import XilinxPlatform
from migen.build.generic_platform import *
from migen.build.xilinx import XilinxPlatform
_ios = [
("clk3", 0, Pins("N8"), IOStandard("LVCMOS33")),

7
mibuild/platforms/de0nano.py → migen/build/platforms/de0nano.py
View file

@ -1,9 +1,10 @@
# This file is Copyright (c) 2013 Florent Kermarrec <florent@enjoy-digital.fr>
# License: BSD
from mibuild.generic_platform import *
from mibuild.altera import AlteraPlatform
from mibuild.altera.programmer import USBBlaster
from migen.build.generic_platform import *
from migen.build.altera import AlteraPlatform
from migen.build.altera.programmer import USBBlaster
_io = [
("clk50", 0, Pins("R8"), IOStandard("3.3-V LVTTL")),

7
mibuild/platforms/kc705.py → migen/build/platforms/kc705.py
View file

@ -1,6 +1,7 @@
from mibuild.generic_platform import *
from mibuild.xilinx import XilinxPlatform, XC3SProg, VivadoProgrammer, iMPACT
from mibuild.xilinx.ise import XilinxISEToolchain
from migen.build.generic_platform import *
from migen.build.xilinx import XilinxPlatform, XC3SProg, VivadoProgrammer, iMPACT
from migen.build.xilinx.ise import XilinxISEToolchain
_io = [
("user_led", 0, Pins("AB8"), IOStandard("LVCMOS15")),

5
mibuild/platforms/lx9_microboard.py → migen/build/platforms/lx9_microboard.py
View file

@ -1,5 +1,6 @@
from mibuild.generic_platform import *
from mibuild.xilinx import XilinxPlatform
from migen.build.generic_platform import *
from migen.build.xilinx import XilinxPlatform
_io = [
("user_btn", 0, Pins("V4"), IOStandard("LVCMOS33"),

7
mibuild/platforms/m1.py → migen/build/platforms/m1.py
View file

@ -1,6 +1,7 @@
from mibuild.generic_platform import *
from mibuild.xilinx import XilinxPlatform
from mibuild.xilinx.programmer import UrJTAG
from migen.build.generic_platform import *
from migen.build.xilinx import XilinxPlatform
from migen.build.xilinx.programmer import UrJTAG
_io = [
("user_led", 0, Pins("B16"), IOStandard("LVCMOS33"), Drive(24), Misc("SLEW=QUIETIO")),

8
mibuild/platforms/mercury.py → migen/build/platforms/mercury.py
View file

@ -1,9 +1,9 @@
# This file is Copyright (c) 2015 William D. Jones <thor0505@comcast.net>
# License: BSD
from mibuild.generic_platform import *
from mibuild.xilinx import XilinxPlatform
from mibuild.xilinx.programmer import XC3SProg
from migen.build.generic_platform import *
from migen.build.xilinx import XilinxPlatform
from migen.build.xilinx.programmer import XC3SProg
_io = [
@ -71,7 +71,7 @@ _connectors = [
]
# Some default useful extensions- use platform.add_extension() to use, e.g.
# from mibuild.platforms import mercury
# from migen.build.platforms import mercury
# plat = mercury.Platform()
# plat.add_extension(mercury.gpio_sram)

4
mibuild/platforms/mimasv2.py → migen/build/platforms/mimasv2.py
View file

@ -1,5 +1,5 @@
from mibuild.generic_platform import *
from mibuild.xilinx import XilinxPlatform
from migen.build.generic_platform import *
from migen.build.xilinx import XilinxPlatform
_io = [

7
mibuild/platforms/minispartan6.py → migen/build/platforms/minispartan6.py
View file

@ -1,9 +1,10 @@
# This file is Copyright (c) 2015 Matt O'Gorman <mog@rldn.net>
# License: BSD
from mibuild.generic_platform import *
from mibuild.xilinx import XilinxPlatform
from mibuild.xilinx.programmer import XC3SProg, FpgaProg
from migen.build.generic_platform import *
from migen.build.xilinx import XilinxPlatform
from migen.build.xilinx.programmer import XC3SProg, FpgaProg
_io = [
("user_led", 0, Pins("P11"), IOStandard("LVCMOS33")),

7
mibuild/platforms/mixxeo.py → migen/build/platforms/mixxeo.py
View file

@ -1,6 +1,7 @@
from mibuild.generic_platform import *
from mibuild.xilinx import XilinxPlatform
from mibuild.xilinx.programmer import UrJTAG
from migen.build.generic_platform import *
from migen.build.xilinx import XilinxPlatform
from migen.build.xilinx.programmer import UrJTAG
_io = [
("user_led", 0, Pins("V5"), IOStandard("LVCMOS33"), Drive(24), Misc("SLEW=QUIETIO")),

5
mibuild/platforms/ml605.py → migen/build/platforms/ml605.py
View file

@ -1,5 +1,6 @@
from mibuild.generic_platform import *
from mibuild.xilinx import XilinxPlatform
from migen.build.generic_platform import *
from migen.build.xilinx import XilinxPlatform
_io = [
# System clock (Differential 200MHz)

7
mibuild/platforms/papilio_pro.py → migen/build/platforms/papilio_pro.py
View file

@ -1,6 +1,7 @@
from mibuild.generic_platform import *
from mibuild.xilinx import XilinxPlatform
from mibuild.xilinx.programmer import XC3SProg
from migen.build.generic_platform import *
from migen.build.xilinx import XilinxPlatform
from migen.build.xilinx.programmer import XC3SProg
_io = [
("user_led", 0, Pins("P112"), IOStandard("LVCMOS33"), Drive(24), Misc("SLEW=QUIETIO")),

7
mibuild/platforms/pipistrello.py → migen/build/platforms/pipistrello.py
View file

@ -1,6 +1,7 @@
from mibuild.generic_platform import *
from mibuild.xilinx import XilinxPlatform
from mibuild.xilinx.programmer import XC3SProg
from migen.build.generic_platform import *
from migen.build.xilinx import XilinxPlatform
from migen.build.xilinx.programmer import XC3SProg
_io = [
("user_led", 0, Pins("V16"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")), # green at hdmi

5
mibuild/platforms/rhino.py → migen/build/platforms/rhino.py
View file

@ -1,5 +1,6 @@
from mibuild.generic_platform import *
from mibuild.xilinx import XilinxPlatform
from migen.build.generic_platform import *
from migen.build.xilinx import XilinxPlatform
_io = [
("user_led", 0, Pins("Y3")),

5
mibuild/platforms/roach.py → migen/build/platforms/roach.py
View file

@ -1,5 +1,6 @@
from mibuild.generic_platform import *
from mibuild.xilinx import XilinxPlatform
from migen.build.generic_platform import *
from migen.build.xilinx import XilinxPlatform
_io = [
("epb", 0,

4
mibuild/platforms/sim.py → migen/build/platforms/sim.py
View file

@ -1,5 +1,5 @@
from mibuild.generic_platform import *
from mibuild.sim import SimPlatform
from migen.build.generic_platform import *
from migen.build.sim import SimPlatform
class SimPins(Pins):

7
mibuild/platforms/usrp_b100.py → migen/build/platforms/usrp_b100.py
View file

@ -1,5 +1,6 @@
from mibuild.generic_platform import *
from mibuild.xilinx import XilinxPlatform
from migen.build.generic_platform import *
from migen.build.xilinx import XilinxPlatform
_io = [
("clk64", 0,
@ -134,7 +135,7 @@ TIMESPEC TS_Pad2Pad = FROM PADS TO PADS 7 ns;
(gpif.ctl, "in"), (gpif.adr, "out"),
(gpif.slwr, "out"), (gpif.sloe, "out"),
(gpif.slrd, "out"), (gpif.pktend, "out")]:
if flen(i) > 1:
if len(i) > 1:
q = "(*)"
else:
q = ""

7
mibuild/platforms/versa.py → migen/build/platforms/versa.py
View file

@ -1,9 +1,10 @@
# This file is Copyright (c) 2013 Florent Kermarrec <florent@enjoy-digital.fr>
# License: BSD
from mibuild.generic_platform import *
from mibuild.lattice import LatticePlatform
from mibuild.lattice.programmer import LatticeProgrammer
from migen.build.generic_platform import *
from migen.build.lattice import LatticePlatform
from migen.build.lattice.programmer import LatticeProgrammer
_io = [
("clk100", 0, Pins("L5"), IOStandard("LVDS25")),

5
mibuild/platforms/zedboard.py → migen/build/platforms/zedboard.py
View file

@ -1,5 +1,6 @@
from mibuild.generic_platform import *
from mibuild.xilinx import XilinxPlatform
from migen.build.generic_platform import *
from migen.build.xilinx import XilinxPlatform
# Bank 34 and 35 voltage depend on J18 jumper setting
_io = [

5
mibuild/platforms/ztex_115d.py → migen/build/platforms/ztex_115d.py
View file

@ -1,5 +1,6 @@
from mibuild.generic_platform import *
from mibuild.xilinx import XilinxPlatform
from migen.build.generic_platform import *
from migen.build.xilinx import XilinxPlatform
_io = [
("clk_fx", 0, Pins("L22"), IOStandard("LVCMOS33")),

1
migen/build/sim/__init__.py Normal file
View file

@ -0,0 +1 @@
from migen.build.sim.platform import SimPlatform

0
mibuild/sim/common.py → migen/build/sim/common.py
View file

0
mibuild/sim/dut_tb.cpp → migen/build/sim/dut_tb.cpp
View file

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