build/efinix/ifacewriter: Cosmetic cleanup (Replace " with ' when possible) and move add_ddr_lvds to the end.
This commit is contained in:
Florent Kermarrec
parent
02c0ed2de7
commit
aec8276cdb
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@ -26,7 +26,7 @@ class InterfaceWriter:
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self.efinity_path = efinity_path
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self.blocks = []
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self.xml_blocks = []
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self.filename = ''
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self.filename = ""
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self.platform = None
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def set_build_params(self, platform, build_name):
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@ -34,15 +34,15 @@ class InterfaceWriter:
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self.platform = platform
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def generate_xml_blocks(self):
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et.register_namespace('efxpt', "http://www.efinixinc.com/peri_design_db")
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tree = et.parse(self.filename + '.peri.xml')
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et.register_namespace("efxpt", "http://www.efinixinc.com/peri_design_db")
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tree = et.parse(self.filename + ".peri.xml")
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root = tree.getroot()
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for block in self.xml_blocks:
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if block['type'] == 'LVDS':
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if block["type"] == "LVDS":
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self.add_ddr_lvds(root, block)
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xml_string = et.tostring(root, 'utf-8')
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xml_string = et.tostring(root, "utf-8")
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reparsed = expatbuilder.parseString(xml_string, False)
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print_string = reparsed.toprettyxml(indent=" ")
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@ -51,45 +51,6 @@ class InterfaceWriter:
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tools.write_to_file("{}.peri.xml".format(self.filename), print_string)
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def add_ddr_lvds(self, root, params):
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lvds_info = root.find('efxpt:lvds_info', namespaces)
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if params['mode'] == 'OUTPUT':
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dir = 'tx'
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mode = 'out'
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else:
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dir = 'rx'
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mode = 'in'
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pad = self.platform.parser.get_gpio_instance_from_pin(params['location'][0])
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pad = pad.replace('TXP', 'TX')
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pad = pad.replace('TXN', 'TX')
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pad = pad.replace('RXP', 'RX')
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pad = pad.replace('RXN', 'RX')
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# Sometimes there is an extra identifier at the end
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# TODO: do a better parser
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if pad.count('_') == 2:
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pad = pad.rsplit('_', 1)[0]
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lvds = et.SubElement(lvds_info, 'efxpt:lvds',
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name = params['name'],
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lvds_def = pad,
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ops_type = dir
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)
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et.SubElement(lvds, 'efxpt:ltx_info',
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pll_instance = '',
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fast_clock_name = '{}'.format(params['fast_clk']),
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slow_clock_name = '{}'.format(params['slow_clk']),
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reset_name = '',
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out_bname = '{}'.format(params['name']),
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oe_name = '',
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clock_div = '1',
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mode = '{}'.format(mode),
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serialization = '{}'.format(params['serialisation']),
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reduced_swing = 'false',
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load = '3'
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)
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def header(self, build_name, partnumber):
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header = "# Autogenerated by LiteX / git: " + tools.get_litex_git_revision()
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header += """
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@ -97,15 +58,15 @@ import os
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import sys
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import pprint
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home = '{0}'
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home = "{0}"
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os.environ['EFXPT_HOME'] = home + '/pt'
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os.environ['EFXPGM_HOME'] = home + '/pgm'
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os.environ['EFXDBG_HOME'] = home + '/debugger'
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os.environ['EFXIPM_HOME'] = home + '/ipm'
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os.environ["EFXPT_HOME"] = home + "/pt"
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os.environ["EFXPGM_HOME"] = home + "/pgm"
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os.environ["EFXDBG_HOME"] = home + "/debugger"
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os.environ["EFXIPM_HOME"] = home + "/ipm"
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sys.path.append(home + '/pt/bin')
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sys.path.append(home + '/lib/python3.8/site-packages')
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sys.path.append(home + "/pt/bin")
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sys.path.append(home + "/lib/python3.8/site-packages")
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from api_service.design import DesignAPI
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from api_service.device import DeviceAPI
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@ -115,105 +76,105 @@ is_verbose = {1}
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design = DesignAPI(is_verbose)
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device = DeviceAPI(is_verbose)
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design.create('{2}', '{3}', './../gateware', overwrite=True)
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design.create("{2}", "{3}", "./../gateware", overwrite=True)
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"""
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return header.format(self.efinity_path, 'True', build_name, partnumber)
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return header.format(self.efinity_path, "True", build_name, partnumber)
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def get_block(self, name):
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for b in self.blocks:
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if b['name'] == name:
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if b["name"] == name:
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return b
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return None
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def generate_gpio(self, block, verbose=True):
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name = block['name']
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mode = block['mode']
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cmd = ''
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name = block["name"]
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mode = block["mode"]
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cmd = ""
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if mode == 'INOUT':
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if len(block['location']) == 1:
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cmd += 'design.create_inout_gpio("{}")\n'.format(name)
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cmd += 'design.assign_pkg_pin("{}","{}")\n'.format(name, block['location'][0])
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if mode == "INOUT":
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if len(block["location"]) == 1:
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cmd += f'design.create_inout_gpio("{name}")\n'
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cmd += f'design.assign_pkg_pin("{name}","{block["location"][0]}")\n'
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else:
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cmd += 'design.create_inout_gpio("{}",{},0)\n'.format(name, block['size']-1)
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for i, pad in enumerate(block['location']):
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cmd += 'design.assign_pkg_pin("{}[{}]","{}")\n'.format(name, i, pad)
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cmd += '\n'
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cmd += f'design.create_inout_gpio("{name}",{block["size"]-1},0)\n'
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for i, pad in enumerate(block["location"]):
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cmd += f'design.assign_pkg_pin("{name}[{i}]","{pad}")\n'
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cmd += "\n"
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return cmd
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if mode == 'INPUT':
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if len(block['location']) == 1:
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cmd += 'design.create_input_gpio("{}")\n'.format(name)
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cmd += 'design.assign_pkg_pin("{}","{}")\n'.format(name, block['location'][0])
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if mode == "INPUT":
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if len(block["location"]) == 1:
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cmd += f'design.create_input_gpio("{name}")\n'
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cmd += f'design.assign_pkg_pin("{name}","{block["location"][0]}")\n'
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else:
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cmd += 'design.create_input_gpio("{}",{},0)\n'.format(name, block['size']-1)
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for i, pad in enumerate(block['location']):
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cmd += 'design.assign_pkg_pin("{}[{}]","{}")\n'.format(name, i, pad)
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if 'in_reg' in block:
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cmd += 'design.set_property("{}","IN_REG","{}")\n'.format(name, block['in_reg'])
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cmd += 'design.set_property("{}","IN_CLK_PIN","{}")\n'.format(name, block['in_clk_pin'])
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cmd += f'design.create_input_gpio("{name}",{block["size"]-1},0)\n'
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for i, pad in enumerate(block["location"]):
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cmd += f'design.assign_pkg_pin("{name}[{i}]","{pad}")\n'
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if "in_reg" in block:
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cmd += f'design.set_property("{name}","IN_REG","{block["in_reg"]}")\n'
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cmd += f'design.set_property("{name}","IN_CLK_PIN","{block["in_clk_pin"]}")\n'
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return cmd
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if mode == 'OUTPUT':
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if len(block['location']) == 1:
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if mode == "OUTPUT":
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if len(block["location"]) == 1:
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cmd += 'design.create_output_gpio("{}")\n'.format(name)
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cmd += 'design.assign_pkg_pin("{}","{}")\n'.format(name, block['location'][0])
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cmd += 'design.assign_pkg_pin("{}","{}")\n'.format(name, block["location"][0])
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else:
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cmd += 'design.create_input_gpio("{}",{},0)\n'.format(name, block['size']-1)
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for i, pad in enumerate(block['location']):
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cmd += 'design.create_input_gpio("{}",{},0)\n'.format(name, block["size"]-1)
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for i, pad in enumerate(block["location"]):
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cmd += 'design.assign_pkg_pin("{}[{}]","{}")\n'.format(name, i, pad)
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if 'out_reg' in block:
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cmd += 'design.set_property("{}","OUT_REG","{}")\n'.format(name, block['out_reg'])
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cmd += 'design.set_property("{}","OUT_CLK_PIN","{}")\n'.format(name, block['out_clk_pin'])
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if "out_reg" in block:
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cmd += 'design.set_property("{}","OUT_REG","{}")\n'.format(name, block["out_reg"])
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cmd += 'design.set_property("{}","OUT_CLK_PIN","{}")\n'.format(name, block["out_clk_pin"])
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if 'drive_strength' in block:
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cmd += 'design.set_property("{}","DRIVE_STRENGTH","4")\n'.format(name, block['drive_strength'])
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if "drive_strength" in block:
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cmd += 'design.set_property("{}","DRIVE_STRENGTH","4")\n'.format(name, block["drive_strength"])
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cmd += '\n'
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cmd += "\n"
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return cmd
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if mode == 'INPUT_CLK':
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if mode == "INPUT_CLK":
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cmd += 'design.create_input_clock_gpio("{}")\n'.format(name)
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cmd += 'design.set_property("{}","IN_PIN","{}")\n'.format(name, name)
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cmd += 'design.assign_pkg_pin("{}","{}")\n\n'.format(name, block['location'])
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cmd += 'design.assign_pkg_pin("{}","{}")\n\n'.format(name, block["location"])
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return cmd
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if mode == 'OUTPUT_CLK':
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if mode == "OUTPUT_CLK":
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cmd += 'design.create_clockout_gpio("{}")\n'.format(name)
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cmd += 'design.set_property("{}","OUT_CLK_PIN","{}")\n'.format(name, name)
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cmd += 'design.assign_pkg_pin("{}","{}")\n\n'.format(name, block['location'])
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cmd += 'design.assign_pkg_pin("{}","{}")\n\n'.format(name, block["location"])
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return cmd
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cmd = '# TODO: ' + str(block) +'\n'
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cmd = "# TODO: " + str(block) +"\n"
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return cmd
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def generate_pll(self, block, partnumber, verbose=True):
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name = block['name']
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cmd = '# ---------- PLL {} ---------\n'.format(name)
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name = block["name"]
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cmd = "# ---------- PLL {} ---------\n".format(name)
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cmd += 'design.create_block("{}", block_type="PLL")\n'.format(name)
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cmd += 'pll_config = {{ "REFCLK_FREQ":"{}" }}\n'.format(block['input_freq'] / 1e6)
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cmd += 'pll_config = {{ "REFCLK_FREQ":"{}" }}\n'.format(block["input_freq"] / 1e6)
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cmd += 'design.set_property("{}", pll_config, block_type="PLL")\n\n'.format(name)
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if block['input_clock'] == 'EXTERNAL':
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if block["input_clock"] == "EXTERNAL":
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# PLL V1 has a different configuration
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if partnumber[0:2] in ["T4", "T8"]:
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cmd += 'design.gen_pll_ref_clock("{}", pll_res="{}", refclk_res="{}", refclk_name="{}", ext_refclk_no="{}")\n\n' \
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.format(name, block['resource'], block['input_clock_pad'], block['input_clock_name'], block['clock_no'])
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.format(name, block["resource"], block["input_clock_pad"], block["input_clock_name"], block["clock_no"])
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else:
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cmd += 'design.gen_pll_ref_clock("{}", pll_res="{}", refclk_src="{}", refclk_name="{}", ext_refclk_no="{}")\n\n' \
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.format(name, block['resource'], block['input_clock'], block['input_clock_name'], block['clock_no'])
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.format(name, block["resource"], block["input_clock"], block["input_clock_name"], block["clock_no"])
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else:
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cmd += 'design.gen_pll_ref_clock("{}", pll_res="{}", refclk_name="{}", refclk_src="CORE")\n'.format(name, block['resource'], block['input_signal'])
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cmd += 'design.set_property("{}", "CORE_CLK_PIN", "{}", block_type="PLL")\n\n'.format(name, block['input_signal'])
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cmd += 'design.gen_pll_ref_clock("{}", pll_res="{}", refclk_name="{}", refclk_src="CORE")\n'.format(name, block["resource"], block["input_signal"])
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cmd += 'design.set_property("{}", "CORE_CLK_PIN", "{}", block_type="PLL")\n\n'.format(name, block["input_signal"])
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cmd += 'design.set_property("{}","LOCKED_PIN","{}", block_type="PLL")\n'.format(name, block['locked'])
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if block['rstn'] != '':
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cmd += 'design.set_property("{}","RSTN_PIN","{}", block_type="PLL")\n\n'.format(name, block['rstn'])
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cmd += 'design.set_property("{}","LOCKED_PIN","{}", block_type="PLL")\n'.format(name, block["locked"])
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if block["rstn"] != "":
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cmd += 'design.set_property("{}","RSTN_PIN","{}", block_type="PLL")\n\n'.format(name, block["rstn"])
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# Output clock 0 is enabled by default
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for i, clock in enumerate(block['clk_out']):
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for i, clock in enumerate(block["clk_out"]):
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if i > 0:
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cmd += 'pll_config = {{ "CLKOUT{}_EN":"1", "CLKOUT{}_PIN":"{}" }}\n'.format(i, i, clock[0])
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else:
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@ -221,18 +182,18 @@ design.create('{2}', '{3}', './../gateware', overwrite=True)
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cmd += 'design.set_property("{}", pll_config, block_type="PLL")\n\n'.format(name)
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for i, clock in enumerate(block['clk_out']):
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for i, clock in enumerate(block["clk_out"]):
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cmd += 'design.set_property("{}","CLKOUT{}_PHASE","{}","PLL")\n'.format(name, i, clock[2])
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cmd += 'target_freq = {\n'
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for i, clock in enumerate(block['clk_out']):
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cmd += "target_freq = {\n"
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for i, clock in enumerate(block["clk_out"]):
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cmd += ' "CLKOUT{}_FREQ": "{}",\n'.format(i, clock[1] / 1e6)
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cmd += '}\n'
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cmd += "}\n"
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cmd += 'calc_result = design.auto_calc_pll_clock("{}", target_freq)\n'.format(name)
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if 'extra' in block:
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cmd += block['extra']
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cmd += '\n'
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if "extra" in block:
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cmd += block["extra"]
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cmd += "\n"
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if verbose:
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cmd += 'print("#### {} ####")\n'.format(name)
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@ -244,15 +205,15 @@ design.create('{2}', '{3}', './../gateware', overwrite=True)
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cmd += 'prop_map = design.get_property("{}", clock_source_prop, block_type="PLL")\n'.format(name)
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cmd += 'pprint.pprint(prop_map)\n'
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cmd += '# ---------- END PLL {} ---------\n\n'.format(name)
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cmd += "# ---------- END PLL {} ---------\n\n".format(name)
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return cmd
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def generate(self, partnumber):
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output = ''
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output = ""
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for b in self.blocks:
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if b['type'] == 'PLL':
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if b["type"] == "PLL":
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output += self.generate_pll(b, partnumber)
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if b['type'] == 'GPIO':
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if b["type"] == "GPIO":
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output += self.generate_gpio(b)
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return output
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@ -264,3 +225,42 @@ design.generate(enable_bitstream=True)
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# Save the configured periphery design
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design.save()"""
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def add_ddr_lvds(self, root, params):
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lvds_info = root.find("efxpt:lvds_info", namespaces)
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if params["mode"] == "OUTPUT":
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dir = "tx"
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mode = "out"
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else:
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dir = "rx"
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mode = "in"
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pad = self.platform.parser.get_gpio_instance_from_pin(params["location"][0])
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pad = pad.replace("TXP", "TX")
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pad = pad.replace("TXN", "TX")
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pad = pad.replace("RXP", "RX")
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pad = pad.replace("RXN", "RX")
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# Sometimes there is an extra identifier at the end
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# TODO: do a better parser
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if pad.count("_") == 2:
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pad = pad.rsplit("_", 1)[0]
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lvds = et.SubElement(lvds_info, "efxpt:lvds",
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name = params["name"],
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lvds_def = pad,
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ops_type = dir
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)
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et.SubElement(lvds, "efxpt:ltx_info",
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pll_instance = "",
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fast_clock_name = "{}".format(params["fast_clk"]),
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slow_clock_name = "{}".format(params["slow_clk"]),
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reset_name = "",
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out_bname = "{}".format(params["name"]),
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oe_name = "",
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clock_div = "1",
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mode = "{}".format(mode),
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serialization = "{}".format(params["serialisation"]),
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reduced_swing = "false",
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load = "3"
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)
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