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mibuild/xilinx: export special_overrides dictionary

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Sebastien Bourdeauducq 2015-03-14 10:45:11 +01:00
parent d34b7d7a6b
commit aef9275c99
2 changed files with 11 additions and 12 deletions
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10
mibuild/xilinx/common.py
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@ -4,6 +4,8 @@ from distutils.version import StrictVersion
from migen.fhdl.std import * from migen.fhdl.std import *
from migen.fhdl.specials import SynthesisDirective from migen.fhdl.specials import SynthesisDirective
from migen.genlib.cdc import * from migen.genlib.cdc import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from migen.genlib.io import *
from mibuild import tools from mibuild import tools
def settings(path, ver=None, sub=None): def settings(path, ver=None, sub=None):
@ -81,3 +83,11 @@ class XilinxDifferentialOutput:
@staticmethod @staticmethod
def lower(dr): def lower(dr):
return XilinxDifferentialOutputImpl(dr.i, dr.o_p, dr.o_n) return XilinxDifferentialOutputImpl(dr.i, dr.o_p, dr.o_n)
xilinx_special_overrides = {
NoRetiming: XilinxNoRetiming,
MultiReg: XilinxMultiReg,
AsyncResetSynchronizer: XilinxAsyncResetSynchronizer,
DifferentialInput: XilinxDifferentialInput,
DifferentialOutput: XilinxDifferentialOutput,
}

13
mibuild/xilinx/platform.py
View file

@ -1,7 +1,3 @@
from migen.genlib.cdc import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from migen.genlib.io import *
from mibuild.generic_platform import GenericPlatform from mibuild.generic_platform import GenericPlatform
from mibuild.xilinx import common, vivado, ise from mibuild.xilinx import common, vivado, ise
@ -18,20 +14,13 @@ class XilinxPlatform(GenericPlatform):
raise ValueError("Unknown toolchain") raise ValueError("Unknown toolchain")
def get_verilog(self, *args, special_overrides=dict(), **kwargs): def get_verilog(self, *args, special_overrides=dict(), **kwargs):
so = { so = dict(common.xilinx_special_overrides)
NoRetiming: common.XilinxNoRetiming,
MultiReg: common.XilinxMultiReg,
AsyncResetSynchronizer: common.XilinxAsyncResetSynchronizer,
DifferentialInput: common.XilinxDifferentialInput,
DifferentialOutput: common.XilinxDifferentialOutput,
}
so.update(special_overrides) so.update(special_overrides)
return GenericPlatform.get_verilog(self, *args, special_overrides=so, **kwargs) return GenericPlatform.get_verilog(self, *args, special_overrides=so, **kwargs)
def get_edif(self, fragment, **kwargs): def get_edif(self, fragment, **kwargs):
return GenericPlatform.get_edif(self, fragment, "UNISIMS", "Xilinx", self.device, **kwargs) return GenericPlatform.get_edif(self, fragment, "UNISIMS", "Xilinx", self.device, **kwargs)
def build(self, *args, **kwargs): def build(self, *args, **kwargs):
return self.toolchain.build(self, *args, **kwargs) return self.toolchain.build(self, *args, **kwargs)