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soc_sdram: add use_full_memory_we parameter to allow disabling vivado workaround on small l2 caches

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Florent Kermarrec 2019-02-12 12:12:40 +01:00
parent 32543430c0
commit af52842fbb
1 changed files with 2 additions and 2 deletions
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4
litex/soc/integration/soc_sdram.py
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@ -55,7 +55,7 @@ class SoCSDRAM(SoCCore):
raise FinalizeError raise FinalizeError
self._wb_sdram_ifs.append(interface) self._wb_sdram_ifs.append(interface)
def register_sdram(self, phy, geom_settings, timing_settings, use_axi=False, **kwargs): def register_sdram(self, phy, geom_settings, timing_settings, use_axi=False, use_full_memory_we=True, **kwargs):
assert not self._sdram_phy assert not self._sdram_phy
self._sdram_phy.append(phy) # encapsulate in list to prevent CSR scanning self._sdram_phy.append(phy) # encapsulate in list to prevent CSR scanning
@ -85,7 +85,7 @@ class SoCSDRAM(SoCCore):
# XXX Vivado ->2018.2 workaround, Vivado is not able to map correctly our L2 cache. # XXX Vivado ->2018.2 workaround, Vivado is not able to map correctly our L2 cache.
# Issue is reported to Xilinx, Remove this if ever fixed by Xilinx... # Issue is reported to Xilinx, Remove this if ever fixed by Xilinx...
from litex.build.xilinx.vivado import XilinxVivadoToolchain from litex.build.xilinx.vivado import XilinxVivadoToolchain
if isinstance(self.platform.toolchain, XilinxVivadoToolchain): if isinstance(self.platform.toolchain, XilinxVivadoToolchain) and use_full_memory_we:
from migen.fhdl.simplify import FullMemoryWE from migen.fhdl.simplify import FullMemoryWE
self.submodules.l2_cache = FullMemoryWE()(l2_cache) self.submodules.l2_cache = FullMemoryWE()(l2_cache)
else: else: