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examples/de1: fix top

This commit is contained in:
Florent Kermarrec 2012-09-12 18:07:36 +02:00
parent fb624fddc4
commit af64beec53
1 changed files with 3 additions and 2 deletions
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5
examples/de1/top.py
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@ -20,7 +20,7 @@
# & Trig |
# Arduino (Uart<-->Spi Bridge)
# |
# De0 Nano
# De1
# |
# +--------------------+-----------------------+
# migIo Signal Generator migLa
@ -112,6 +112,7 @@ def get():
]
# Dat / Trig Bus
comb += [
trigger0.in_trig.eq(sig_gen),
@ -137,7 +138,7 @@ def get():
cst = Constraints(in_clk, in_rst_n, spi2csr0, led0)
src_verilog, vns = verilog.convert(frag,
cst.get_ios(),
name="de0_nano",
name="de1",
clk_signal = in_clk,
rst_signal = in_rst,
return_ns=True)