efinix: common: replace `is_inclk_inverted`
replace `is_inclk_inverted` with `in_clk_inv` and `out_clk_inv`. This way thwe right prop is set in the ifacewriter.py. Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
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@ -295,7 +295,8 @@ class EfinixDDRTristateImpl(Module):
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"out_reg" : "DDIO_RESYNC",
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"out_reg" : "DDIO_RESYNC",
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"out_clk_pin" : clk,
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"out_clk_pin" : clk,
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"oe_reg" : "REG",
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"oe_reg" : "REG",
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"is_inclk_inverted" : False,
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"in_clk_inv" : 0,
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"out_clk_inv" : 0,
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"drive_strength" : io_prop_dict.get("DRIVE_STRENGTH", "4")
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"drive_strength" : io_prop_dict.get("DRIVE_STRENGTH", "4")
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}
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}
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platform.toolchain.ifacewriter.blocks.append(block)
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platform.toolchain.ifacewriter.blocks.append(block)
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@ -333,7 +334,8 @@ class EfinixSDRTristateImpl(EfinixDDRTristateImpl):
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"out_reg" : "REG",
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"out_reg" : "REG",
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"out_clk_pin" : clk,
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"out_clk_pin" : clk,
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"oe_reg" : "REG",
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"oe_reg" : "REG",
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"is_inclk_inverted" : False,
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"in_clk_inv" : 0,
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"out_clk_inv" : 0,
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"drive_strength" : io_prop_dict.get("DRIVE_STRENGTH", "4")
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"drive_strength" : io_prop_dict.get("DRIVE_STRENGTH", "4")
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}
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}
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platform.toolchain.ifacewriter.blocks.append(block)
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platform.toolchain.ifacewriter.blocks.append(block)
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@ -365,7 +367,7 @@ class EfinixSDROutputImpl(Module):
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"size" : 1,
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"size" : 1,
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"out_reg" : "REG",
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"out_reg" : "REG",
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"out_clk_pin" : clk,
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"out_clk_pin" : clk,
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"is_inclk_inverted" : False,
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"out_clk_inv" : 0,
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"drive_strength" : io_prop_dict.get("DRIVE_STRENGTH", "4")
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"drive_strength" : io_prop_dict.get("DRIVE_STRENGTH", "4")
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}
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}
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platform.toolchain.ifacewriter.blocks.append(block)
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platform.toolchain.ifacewriter.blocks.append(block)
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@ -399,7 +401,7 @@ class EfinixDDROutputImpl(Module):
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"size" : 1,
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"size" : 1,
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"out_reg" : "DDIO_RESYNC",
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"out_reg" : "DDIO_RESYNC",
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"out_clk_pin" : clk,
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"out_clk_pin" : clk,
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"is_inclk_inverted" : False,
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"out_clk_inv" : 0,
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"drive_strength" : io_prop_dict.get("DRIVE_STRENGTH", "4")
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"drive_strength" : io_prop_dict.get("DRIVE_STRENGTH", "4")
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}
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}
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platform.toolchain.ifacewriter.blocks.append(block)
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platform.toolchain.ifacewriter.blocks.append(block)
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@ -460,7 +462,7 @@ class EfinixDDRInputImpl(Module):
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"size" : 1,
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"size" : 1,
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"in_reg" : "DDIO_RESYNC",
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"in_reg" : "DDIO_RESYNC",
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"in_clk_pin" : clk,
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"in_clk_pin" : clk,
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"is_inclk_inverted" : False
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"in_clk_inv" : 0
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}
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}
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platform.toolchain.ifacewriter.blocks.append(block)
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platform.toolchain.ifacewriter.blocks.append(block)
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platform.toolchain.excluded_ios.append(platform.get_pin(i))
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platform.toolchain.excluded_ios.append(platform.get_pin(i))
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