enjoy-digital
GitHub
commit
b033d91738
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from litex.soc.cores.cpu.cva6.core import CVA6
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@ -0,0 +1,18 @@
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.section .text, "ax", @progbits
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.global boot_helper
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.global smp_ap_args
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.global smp_ap_target
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.global smp_ap_ready
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boot_helper:
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// boot core saves args and jump target for ap cores:
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sd a0, smp_ap_args, t1
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sd a1, smp_ap_args+8, t1
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sd a2, smp_ap_args+16, t1
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sd a3, smp_ap_target, t1
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fence w, w
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// notify application cores to proceed with boot:
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li t0, 1
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sd t0, smp_ap_ready, t1
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// boot core now also ready to boot:
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jr a3
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@ -0,0 +1,196 @@
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#
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# This file is part of LiteX.
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#
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# Copyright (c) 2021 Hensoldt Cyber GmbH <www.hensoldt-cyber.com>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import re
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from migen import *
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from migen.fhdl.specials import Tristate
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from litex import get_data_mod
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from litex.soc.interconnect import axi
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from litex.soc.interconnect import wishbone, stream
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from litex.soc.interconnect.csr import *
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from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV64
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class Open(Signal): pass
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# Variants -----------------------------------------------------------------------------------------
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CPU_VARIANTS = ["standard", "full"]
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# GCC Flags ----------------------------------------------------------------------------------------
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GCC_FLAGS = {
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# /-------- Base ISA
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# |/------- Hardware Multiply + Divide
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# ||/----- Atomics
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# |||/---- Compressed ISA
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# ||||/--- Single-Precision Floating-Point
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# |||||/-- Double-Precision Floating-Point
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# imacfd
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"standard": "-march=rv64imac -mabi=lp64 ",
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"full": "-march=rv64gc -mabi=lp64 ",
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}
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# Helpers ------------------------------------------------------------------------------------------
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def add_manifest_sources(platform, manifest):
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# TODO: create a pythondata-cpu-cva6 package to be installed with litex, then use this generic comment
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basedir = get_data_mod("cpu", "cva6").data_location
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with open(os.path.join(basedir, manifest), 'r') as f:
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for l in f:
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res = re.search('\$\{CVA6_REPO_DIR\}/(.+)', l)
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if res and not re.match('//', l):
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if re.match('\+incdir\+', l):
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platform.add_verilog_include_path(os.path.join(basedir, res.group(1)))
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else:
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platform.add_source(os.path.join(basedir, res.group(1)))
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# CVA6 -----------------------------------------------------------------------------------------
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class CVA6(CPU):
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family = "riscv"
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name = "cva6"
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human_name = "CVA6"
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variants = CPU_VARIANTS
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data_width = 64
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endianness = "little"
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gcc_triple = CPU_GCC_TRIPLE_RISCV64
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linker_output_format = "elf64-littleriscv"
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nop = "nop"
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io_regions = {0x80000000: 0x80000000} # Origin, Length.
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has_fpu = ["full"]
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# GCC Flags.
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@property
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def gcc_flags(self):
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flags = GCC_FLAGS[self.variant]
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flags += "-D__cva6__ "
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flags += f" -DUART_POLLING"
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return flags
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# Memory Mapping.
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@property
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def mem_map(self):
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return {
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"rom" : 0x10000000,
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"sram" : 0x20000000,
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"csr" : 0x80000000
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}
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jtag_layout = [
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("tck", 1),
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("tms", 1),
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("trst", 1),
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("tdi", 1),
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("tdo", 1),
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]
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def __init__(self, platform, variant="standard"):
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self.platform = platform
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self.variant = variant
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data_width = 64
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self.axi_if = axi_if = axi.AXIInterface(data_width=data_width, address_width=data_width, id_width=4)
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wb_if = wishbone.Interface(data_width=data_width, adr_width=data_width-log2_int(data_width//8))
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a2w = axi.AXI2Wishbone(axi_if, wb_if, base_address=0x00000000)
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self.submodules += a2w
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self.memory_buses = []
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self.periph_buses = [wb_if]
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self.interrupt = Signal(32)
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self.reset = Signal()
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tdo_i = Signal()
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tdo_o = Signal()
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tdo_oe = Signal()
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pads = Record(self.jtag_layout)
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self.pads = pads
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self.specials += Tristate(pads.tdo, tdo_o, tdo_oe, tdo_i)
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self.cpu_params = dict(
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# Clk / Rst.
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i_clk_i = ClockSignal("sys"),
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i_rst_n = ~ResetSignal("sys"),
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# Interrupts
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i_irq_sources = self.interrupt,
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# AXI interface
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o_AWID_o = axi_if.aw.id,
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o_AWADDR_o = axi_if.aw.addr,
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o_AWLEN_o = axi_if.aw.len,
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o_AWSIZE_o = axi_if.aw.size,
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o_AWBURST_o = axi_if.aw.burst,
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o_AWLOCK_o = axi_if.aw.lock,
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o_AWCACHE_o = axi_if.aw.cache,
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o_AWPROT_o = axi_if.aw.prot,
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o_AWQOS_o = axi_if.aw.qos,
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o_AWREGION_o = Open(),
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o_AWUSER_o = Open(),
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o_AWVALID_o = axi_if.aw.valid,
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o_WDATA_o = axi_if.w.data,
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o_WSTRB_o = axi_if.w.strb,
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o_WLAST_o = axi_if.w.last,
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o_WUSER_o = Open(),
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o_WVALID_o = axi_if.w.valid,
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o_BREADY_o = axi_if.b.ready,
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o_ARID_o = axi_if.ar.id,
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o_ARADDR_o = axi_if.ar.addr,
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o_ARLEN_o = axi_if.ar.len,
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o_ARSIZE_o = axi_if.ar.size,
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o_ARBURST_o = axi_if.ar.burst,
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o_ARLOCK_o = axi_if.ar.lock,
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o_ARCACHE_o = axi_if.ar.cache,
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o_ARPROT_o = axi_if.ar.prot,
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o_ARQOS_o = axi_if.ar.qos,
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o_ARUSER_o = Open(),
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o_ARREGION_o = Open(),
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o_ARVALID_o = axi_if.ar.valid,
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o_RREADY_o = axi_if.r.ready,
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i_AWREADY_i = axi_if.aw.ready,
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i_ARREADY_i = axi_if.ar.ready,
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i_WREADY_i = axi_if.w.ready,
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i_BVALID_i = axi_if.b.valid,
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i_BID_i = axi_if.b.id,
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i_BRESP_i = axi_if.b.resp,
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i_BUSER_i = 0,
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i_RVALID_i = axi_if.r.valid,
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i_RID_i = axi_if.r.id,
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i_RDATA_i = axi_if.r.data,
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i_RRESP_i = axi_if.r.resp,
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i_RLAST_i = axi_if.r.last,
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i_RUSER_i = 0,
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# JTAG.
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i_trst_n = pads.trst,
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i_tck = pads.tck,
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i_tms = pads.tms,
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i_tdi = pads.tdi,
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o_tdo = tdo_o,
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o_tdo_oe = tdo_oe,
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# TODO: add trace interface
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)
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# Add Verilog sources.
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# TODO: use Flist.cv64a6_imafdc_sv39 and Flist.cv32a6_imac_sv0 instead
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add_manifest_sources(platform, 'Flist.cv64a6_imafdc_sv39')
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add_manifest_sources(platform, 'Flist.cva6_wrapper')
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def set_reset_address(self, reset_address):
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self.reset_address = reset_address
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assert reset_address == 0x10000000, "cpu_reset_addr hardcoded in during elaboration!"
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def do_finalize(self):
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assert hasattr(self, "reset_address")
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self.specials += Instance("cva6_wrapper", **self.cpu_params)
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@ -0,0 +1,125 @@
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.global main
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.global isr
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.global _start
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.global smp_ap_args
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.global smp_ap_target
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.global smp_ap_ready
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_start:
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j crt_init
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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trap_entry:
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sd x1, - 1*8(sp)
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sd x5, - 2*8(sp)
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sd x6, - 3*8(sp)
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sd x7, - 4*8(sp)
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sd x10, - 5*8(sp)
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sd x11, - 6*8(sp)
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sd x12, - 7*8(sp)
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sd x13, - 8*8(sp)
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sd x14, - 9*8(sp)
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sd x15, -10*8(sp)
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sd x16, -11*8(sp)
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sd x17, -12*8(sp)
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sd x28, -13*8(sp)
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sd x29, -14*8(sp)
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sd x30, -15*8(sp)
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sd x31, -16*8(sp)
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addi sp,sp,-16*8
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call isr
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ld x1 , 15*8(sp)
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ld x5, 14*8(sp)
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ld x6, 13*8(sp)
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ld x7, 12*8(sp)
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ld x10, 11*8(sp)
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ld x11, 10*8(sp)
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ld x12, 9*8(sp)
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ld x13, 8*8(sp)
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ld x14, 7*8(sp)
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ld x15, 6*8(sp)
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ld x16, 5*8(sp)
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ld x17, 4*8(sp)
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ld x28, 3*8(sp)
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ld x29, 2*8(sp)
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ld x30, 1*8(sp)
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ld x31, 0*8(sp)
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addi sp,sp,16*8
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mret
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.text
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crt_init:
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la sp, _fstack
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sd zero, smp_ap_ready, t0
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la t0, trap_entry
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csrw mtvec, t0
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smp_select_bp:
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csrr a0, mhartid
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beqz a0, data_init // hart 0 is bp, everyone else is ap
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smp_ap_loop:
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ld t0, smp_ap_ready
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beqz t0, smp_ap_loop
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smp_ap_boot:
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fence r, r
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fence.i // i$ flush
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ld a0, smp_ap_args // hart ID (but next-stage loads its own)
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ld a1, smp_ap_args+8 // DTB pointer (if provded by litex bios)
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ld a2, smp_ap_args+16
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ld a3, smp_ap_target
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jr a3
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smp_ap_done:
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data_init:
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la t0, _fdata
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la t1, _edata
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la t2, _fdata_rom
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data_loop:
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beq t0,t1,data_done
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ld t3,0(t2)
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sd t3,0(t0)
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add t0,t0,8
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add t2,t2,8
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j data_loop
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data_done:
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bss_init:
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la t0, _fbss
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la t1, _ebss
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bss_loop:
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beq t0,t1,bss_done
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sd zero,0(t0)
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add t0,t0,8
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j bss_loop
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bss_done:
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// call plic_init // initialize external interrupt controller
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li t0, 0x800 // external interrupt sources only (using LiteX timer);
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// NOTE: must still enable mstatus.MIE!
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csrw mie,t0
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call main
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inf_loop:
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j inf_loop
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.bss
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.align 8
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smp_ap_args:
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.dword 0
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.dword 0
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.dword 0
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.align 8
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smp_ap_target:
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.dword 0
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.align 8
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smp_ap_ready:
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.dword 0
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@ -0,0 +1,8 @@
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#ifndef CSR_DEFS__H
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#define CSR_DEFS__H
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#define CSR_MSTATUS_MIE 0x8
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#define CSR_DCACHE_INFO 0xCC0
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#endif /* CSR_DEFS__H */
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@ -0,0 +1,41 @@
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#ifndef __IRQ_H
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#define __IRQ_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <system.h>
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#include <generated/csr.h>
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#include <generated/soc.h>
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static inline unsigned int irq_getie(void)
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{
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return 0;
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}
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static inline void irq_setie(unsigned int ie)
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{
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}
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static inline unsigned int irq_getmask(void)
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{
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return 0;
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}
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static inline void irq_setmask(unsigned int mask)
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{
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}
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static inline unsigned int irq_pending(void)
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{
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return 0;
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}
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#ifdef __cplusplus
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}
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#endif
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#endif /* __IRQ_H */
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@ -0,0 +1,43 @@
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#ifndef __SYSTEM_H
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#define __SYSTEM_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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__attribute__((unused)) static void flush_cpu_icache(void){} /* FIXME: do something useful here! */
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__attribute__((unused)) static void flush_cpu_dcache(void){}; /* FIXME: do something useful here! */
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void flush_l2_cache(void);
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void busy_wait(unsigned int ms);
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void busy_wait_us(unsigned int us);
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#include <csr-defs.h>
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#define csrr(reg) ({ unsigned long __tmp; \
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asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
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__tmp; })
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#define csrw(reg, val) ({ \
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if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
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asm volatile ("csrw " #reg ", %0" :: "i"(val)); \
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else \
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asm volatile ("csrw " #reg ", %0" :: "r"(val)); })
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#define csrs(reg, bit) ({ \
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if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
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asm volatile ("csrrs x0, " #reg ", %0" :: "i"(bit)); \
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else \
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asm volatile ("csrrs x0, " #reg ", %0" :: "r"(bit)); })
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#define csrc(reg, bit) ({ \
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if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
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asm volatile ("csrrc x0, " #reg ", %0" :: "i"(bit)); \
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else \
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asm volatile ("csrrc x0, " #reg ", %0" :: "r"(bit)); })
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#ifdef __cplusplus
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}
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#endif
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#endif /* __SYSTEM_H */
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|
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@ -106,6 +106,7 @@ git_repos = {
|
|||
"pythondata-cpu-blackparrot": GitRepo(url="https://github.com/litex-hub/"),
|
||||
"pythondata-cpu-cv32e40p": GitRepo(url="https://github.com/litex-hub/", clone="recursive"),
|
||||
"pythondata-cpu-cv32e41p": GitRepo(url="https://github.com/litex-hub/", clone="recursive"),
|
||||
"pythondata-cpu-cva6": GitRepo(url="https://github.com/suppamax/", clone="recursive"),
|
||||
"pythondata-cpu-ibex": GitRepo(url="https://github.com/litex-hub/", clone="recursive", sha1=0xd3d53df),
|
||||
"pythondata-cpu-marocchino": GitRepo(url="https://github.com/litex-hub/"),
|
||||
}
|
||||
|
|
|
|||
|
|
@ -56,6 +56,9 @@ class TestCPU(unittest.TestCase):
|
|||
def test_picorv32(self):
|
||||
self.assertTrue(self.boot_test("picorv32"))
|
||||
|
||||
def test_cva6(self):
|
||||
self.assertTrue(self.boot_test("cva6"))
|
||||
|
||||
# OpenRISC CPUs.
|
||||
#def test_mor1kx(self):
|
||||
# self.assertTrue(self.boot_test("mor1kx"))
|
||||
|
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|
|||
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Reference in New Issue