Merge pull request #79 from xobs/fix-vexriscv-data-read

vexriscv: debug: fix reading DATA register
2018-07-06 13:23:08 +02:00 · 2018-07-06 13:23:08 +02:00 · b062d4dddc
parent e35be26ebf be8eb5ff84
commit b062d4dddc
1 changed files with 1 additions and 1 deletions
--- a/litex/soc/cores/cpu/vexriscv/core.py
+++ b/litex/soc/cores/cpu/vexriscv/core.py
@ -95,7 +95,7 @@ class VexRiscv(Module, AutoCSR):
                # A write to the REFRESH register indicates which register
                # (DATA or CORE) we want to update from the CPU.
                ).Elif(debug_refresh.re,
-                    If(~debug_refresh.storage,
+                    If(debug_refresh.storage == 0,
                        refreshing_data.eq(0),
                        debug_bus_cmd_payload_address.eq(0)
                    ).Else(