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Merge pull request #79 from xobs/fix-vexriscv-data-read 

vexriscv: debug: fix reading DATA register
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enjoy-digital 2018-07-06 13:23:08 +02:00 committed by GitHub
parent e35be26ebf be8eb5ff84
commit b062d4dddc
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litex/soc/cores/cpu/vexriscv/core.py
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@ -95,7 +95,7 @@ class VexRiscv(Module, AutoCSR):
# A write to the REFRESH register indicates which register # A write to the REFRESH register indicates which register
# (DATA or CORE) we want to update from the CPU. # (DATA or CORE) we want to update from the CPU.
).Elif(debug_refresh.re, ).Elif(debug_refresh.re,
If(~debug_refresh.storage, If(debug_refresh.storage == 0,
refreshing_data.eq(0), refreshing_data.eq(0),
debug_bus_cmd_payload_address.eq(0) debug_bus_cmd_payload_address.eq(0)
).Else( ).Else(