xilinx_ise: support building files without running ISE
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7b8e8a19f3
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b092237fa6
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@ -60,7 +60,7 @@ def _build_ucf(named_sc, named_pc):
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r += "\n" + "\n\n".join(named_pc)
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return r
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def _build(device, sources, named_sc, named_pc, build_name, xilinx_install_path):
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def _build_files(device, sources, named_sc, named_pc, build_name):
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tools.write_to_file(build_name + ".ucf", _build_ucf(named_sc, named_pc))
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prj_contents = ""
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@ -78,6 +78,7 @@ def _build(device, sources, named_sc, named_pc, build_name, xilinx_install_path)
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-p %s""" % (build_name, build_name, device)
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tools.write_to_file(build_name + ".xst", xst_contents)
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def _run_ise(build_name, xilinx_install_path):
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def is_valid_version(v):
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try:
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Decimal(v)
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@ -109,7 +110,7 @@ bitgen -g Binary:Yes -w {build_name}-routed.ncd {build_name}.bit
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class XilinxISEPlatform(GenericPlatform):
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def build(self, fragment, clock_domains=None, build_dir="build", build_name="top",
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xilinx_install_path="/opt/Xilinx"):
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xilinx_install_path="/opt/Xilinx", run=True):
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tools.mkdir_noerror(build_dir)
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os.chdir(build_dir)
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@ -117,6 +118,8 @@ class XilinxISEPlatform(GenericPlatform):
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v_file = build_name + ".v"
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tools.write_to_file(v_file, v_src)
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sources = self.sources + [(v_file, "verilog")]
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_build(self.device, sources, named_sc, named_pc, build_name, xilinx_install_path)
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_build_files(self.device, sources, named_sc, named_pc, build_name)
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if run:
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_run_ise(build_name, xilinx_install_path)
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os.chdir("..")
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