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soc/cores/spi: make cs/loopback CSR optional. 

Useful for API retro-compatibility.
This commit is contained in:
Florent Kermarrec 2020-06-19 14:17:30 +02:00
parent 05cb5f96a1
commit b0b37b4cb9
1 changed files with 9 additions and 9 deletions
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18
litex/soc/cores/spi.py
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@ -127,7 +127,7 @@ class SPIMaster(Module, AutoCSR):
) )
] ]
def add_csr(self): def add_csr(self, with_cs=True, with_loopback=True):
self._control = CSRStorage(fields=[ self._control = CSRStorage(fields=[
CSRField("start", size=1, offset=0, pulse=True, description="Write ``1`` to start SPI Xfer"), CSRField("start", size=1, offset=0, pulse=True, description="Write ``1`` to start SPI Xfer"),
CSRField("length", size=8, offset=8, description="SPI Xfer length (in bits).") CSRField("length", size=8, offset=8, description="SPI Xfer length (in bits).")
@ -137,21 +137,21 @@ class SPIMaster(Module, AutoCSR):
], description="SPI Status.") ], description="SPI Status.")
self._mosi = CSRStorage(self.data_width, reset_less=True, description="SPI MOSI data (MSB-first serialization).") self._mosi = CSRStorage(self.data_width, reset_less=True, description="SPI MOSI data (MSB-first serialization).")
self._miso = CSRStatus(self.data_width, description="SPI MISO data (MSB-first de-serialization).") self._miso = CSRStatus(self.data_width, description="SPI MISO data (MSB-first de-serialization).")
self._cs = CSRStorage(fields=[
CSRField("sel", len(self.cs), reset=1, description="Write ``1`` to corresponding bit to enable Xfer for chip.")
], description="SPI Chip Select.")
self._loopback = CSRStorage(description="SPI loopback mode.\n\n Write ``1`` to enable MOSI to MISO internal loopback.")
self.comb += [ self.comb += [
self.start.eq(self._control.fields.start), self.start.eq(self._control.fields.start),
self.length.eq(self._control.fields.length), self.length.eq(self._control.fields.length),
self.mosi.eq(self._mosi.storage), self.mosi.eq(self._mosi.storage),
self.cs.eq(self._cs.storage),
self.loopback.eq(self._loopback.storage),
self._status.fields.done.eq(self.done), self._status.fields.done.eq(self.done),
self._miso.status.eq(self.miso), self._miso.status.eq(self.miso),
] ]
if with_cs:
self._cs = CSRStorage(fields=[
CSRField("sel", len(self.cs), reset=1, description="Write ``1`` to corresponding bit to enable Xfer for chip.")
], description="SPI Chip Select.")
self.comb += self.cs.eq(self._cs.storage)
if with_loopback:
self._loopback = CSRStorage(description="SPI loopback mode.\n\n Write ``1`` to enable MOSI to MISO internal loopback.")
self.comb += self.loopback.eq(self._loopback.storage)
def add_clk_divider(self): def add_clk_divider(self):
self._clk_divider = CSRStorage(16, description="SPI Clk Divider.", reset=self.clk_divider.reset) self._clk_divider = CSRStorage(16, description="SPI Clk Divider.", reset=self.clk_divider.reset)