genlib: add reset synchronizer

mibuild/xilinx_common.py

@@ -4,6 +4,7 @@ from distutils.version import StrictVersion
 from migen.fhdl.std import *
 from migen.fhdl.specials import SynthesisDirective
 from migen.genlib.cdc import *
+from migen.genlib.resetsync import AsyncResetSynchronizer
 from mibuild.generic_platform import GenericPlatform
 from mibuild import tools
 
@@ -66,13 +67,29 @@ class XilinxMultiReg:
 	def lower(dr):
 		return XilinxMultiRegImpl(dr.i, dr.o, dr.odomain, dr.n)
 
+class XilinxAsyncResetSynchronizerImpl(Module):
+	def __init__(self, cd, async_reset):
+		rst1 = Signal()
+		self.specials += [
+			Instance("FDPE", p_INIT=1, i_D=0, i_PRE=async_reset,
+				i_C=cd.clk, o_Q=rst1),
+			Instance("FDPE", p_INIT=1, i_D=rst1, i_PRE=async_reset,
+				i_C=cd.clk, o_Q=cd.rst)
+		]
+
+class XilinxAsyncResetSynchronizer:
+	staticmethod
+	def lower(dr):
+		return XilinxAsyncResetSynchronizerImpl(dr.cd, dr.async_reset)
+
 class XilinxGenericPlatform(GenericPlatform):
 	bitstream_ext = ".bit"
 
 	def get_verilog(self, *args, special_overrides=dict(), **kwargs):
 		so = {
-			NoRetiming: XilinxNoRetiming,
-			MultiReg:   XilinxMultiReg
+			NoRetiming:					XilinxNoRetiming,
+			MultiReg:					XilinxMultiReg,
+			AsyncResetSynchronizer:		XilinxAsyncResetSynchronizer
 		}
 		so.update(special_overrides)
 		return GenericPlatform.get_verilog(self, *args, special_overrides=so, **kwargs)

migen/genlib/resetsync.py

@@ -0,0 +1,18 @@
+from migen.fhdl.std import *
+from migen.fhdl.specials import Special
+from migen.fhdl.tools import list_signals
+
+class AsyncResetSynchronizer(Special):
+	def __init__(self, cd, async_reset):
+		Special.__init__(self)
+		self.cd = cd
+		self.async_reset = async_reset
+		
+	def iter_expressions(self):
+		yield self.cd, "clk", SPECIAL_INPUT
+		yield self.cd, "rst", SPECIAL_OUTPUT
+		yield self, "async_reset", SPECIAL_INPUT
+
+	@staticmethod
+	def lower(dr):
+		raise NotImplementedError("Attempted to use a reset synchronizer, but platform does not support them")