Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

uart/sim: add pty (optional, to use flterm)

This commit is contained in:
Florent Kermarrec 2015-03-09 23:29:06 +01:00
parent 6cbf13036b
commit b157031e8a
1 changed files with 13 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
misoclib/com/uart/phy/sim.py
View File

@ -1,3 +1,5 @@
import os, pty, time
from migen.fhdl.std import * from migen.fhdl.std import *
from migen.flow.actor import Sink, Source from migen.flow.actor import Sink, Source
@ -15,3 +17,14 @@ class UARTPHYSim(Module):
self.source.data.eq(pads.sink_data), self.source.data.eq(pads.sink_data),
pads.sink_ack.eq(self.source.ack) pads.sink_ack.eq(self.source.ack)
] ]
m, s = pty.openpty()
name = os.ttyname(s)
print("UART tty: "+name)
time.sleep(0.5) # pause for user
f = open("/tmp/simserial", "w")
f.write(os.ttyname(s))
f.close()
def do_exit(self, *args, **kwargs):
os.remove("/tmp/simserial")