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interconnect/axi: add missing axi signals

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This commit is contained in:
Florent Kermarrec 2019-04-01 10:23:05 +02:00
parent f95748d167
commit b15fd9d834
1 changed files with 10 additions and 5 deletions
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11
litex/soc/interconnect/axi.py
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@ -20,13 +20,18 @@ def ax_description(address_width, id_width):
("burst", 2), # Burst type
("len", 8), # Number of data (-1) transfers (up to 256)
("size", 4), # Number of bytes (-1) of each data transfer (up to 1024 bits)
("lock", 2),
("prot", 3),
("cache", 4),
("qos", 4),
("id", id_width)
]
def w_description(data_width):
def w_description(data_width, id_width):
return [
("data", data_width),
("strb", data_width//8)
("strb", data_width//8),
("id", id_width)
]
def b_description(id_width):
@ -51,7 +56,7 @@ class AXIInterface(Record):
self.clock_domain = clock_domain
self.aw = stream.Endpoint(ax_description(address_width, id_width))
self.w = stream.Endpoint(w_description(data_width))
self.w = stream.Endpoint(w_description(data_width, id_width))
self.b = stream.Endpoint(b_description(id_width))
self.ar = stream.Endpoint(ax_description(address_width, id_width))
self.r = stream.Endpoint(r_description(data_width, id_width))