Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Merge pull request #313 from mmicko/yosys_ise_flow_fix 

Yosys - ISE flow fix
This commit is contained in:
Tim Ansell 2019-12-05 19:05:44 -08:00 committed by GitHub
parent 8d90f4e97b 783dfa508c
commit b17dfafa55
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 17 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
litex/build/xilinx/ise.py
View File

@ -85,9 +85,17 @@ def _run_yosys(device, sources, vincpaths, build_name):
for filename, language, library in sources: for filename, language, library in sources:
ys_contents += "read_{}{} {}\n".format(language, incflags, filename) ys_contents += "read_{}{} {}\n".format(language, incflags, filename)
ys_contents += """hierarchy -check -top top family = ""
proc; memory; opt; fsm; opt if (device.startswith("xc7") or device.startswith("xa7") or device.startswith("xq7")):
synth_xilinx -top top -edif {build_name}.edif""".format(build_name=build_name) family = "xc7"
elif (device.startswith("xc6s") or device.startswith("xa6s") or device.startswith("xq6s")):
family = "xc6s"
else:
raise OSError("Unsupported device")
ys_contents += """hierarchy -top top
synth_xilinx -top top -family {family} -ise
write_edif -pvector bra {build_name}.edif""".format(build_name=build_name, family=family)
ys_name = build_name + ".ys" ys_name = build_name + ".ys"
tools.write_to_file(ys_name, ys_contents) tools.write_to_file(ys_name, ys_contents)
@ -114,7 +122,10 @@ def _run_ise(build_name, ise_path, source, mode, ngdbuild_opt,
settings = common.settings(ise_path, ver, "ISE_DS") settings = common.settings(ise_path, ver, "ISE_DS")
build_script_contents += source_cmd + tools.cygpath(settings) + "\n" build_script_contents += source_cmd + tools.cygpath(settings) + "\n"
if mode == "edif": if mode == "edif":
ext = "edif" ext = "ngo"
build_script_contents += """
edif2ngd {build_name}.edif {build_name}.{ext}{fail_stmt}
"""
else: else:
ext = "ngc" ext = "ngc"
build_script_contents += """ build_script_contents += """
@ -207,6 +218,7 @@ class XilinxISEToolchain:
_build_xst_files(platform.device, platform.sources, platform.verilog_include_paths, build_name, self.xst_opt) _build_xst_files(platform.device, platform.sources, platform.verilog_include_paths, build_name, self.xst_opt)
isemode = mode isemode = mode
else: else:
if run:
_run_yosys(platform.device, platform.sources, platform.verilog_include_paths, build_name) _run_yosys(platform.device, platform.sources, platform.verilog_include_paths, build_name)
isemode = "edif" isemode = "edif"
ngdbuild_opt += "-p " + platform.device ngdbuild_opt += "-p " + platform.device