axi/axi_lite_to_wishbone: Add different address shift when Wishbone is byte/word addressed.
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@ -17,10 +17,15 @@ from litex.soc.interconnect.axi.axi_lite import *
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class AXILite2Wishbone(LiteXModule):
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def __init__(self, axi_lite, wishbone, base_address=0x00000000):
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wishbone_adr_shift = log2_int(axi_lite.data_width//8)
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# Parameters/Checks.
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wishbone_adr_shift = {
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"word" : log2_int(axi_lite.data_width//8),
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"byte" : 0
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}[wishbone.addressing]
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assert axi_lite.data_width == len(wishbone.dat_r)
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assert axi_lite.address_width == len(wishbone.adr) + wishbone_adr_shift
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# Signals.
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_data = Signal(axi_lite.data_width)
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_r_addr = Signal(axi_lite.address_width)
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_w_addr = Signal(axi_lite.address_width)
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@ -28,6 +33,7 @@ class AXILite2Wishbone(LiteXModule):
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self.comb += _r_addr.eq(axi_lite.ar.addr - base_address)
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self.comb += _w_addr.eq(axi_lite.aw.addr - base_address)
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# FSM.
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self.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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If(axi_lite.ar.valid & axi_lite.aw.valid,
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@ -92,15 +98,21 @@ class AXILite2Wishbone(LiteXModule):
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class Wishbone2AXILite(LiteXModule):
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def __init__(self, wishbone, axi_lite, base_address=0x00000000):
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wishbone_adr_shift = log2_int(axi_lite.data_width//8)
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# Parameters/Checks.
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wishbone_adr_shift = {
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"word" : log2_int(axi_lite.data_width//8),
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"byte" : 0
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}[wishbone.addressing]
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assert axi_lite.data_width == len(wishbone.dat_r)
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assert axi_lite.address_width == len(wishbone.adr) + wishbone_adr_shift
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# Signals.
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_cmd_done = Signal()
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_data_done = Signal()
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_addr = Signal(len(wishbone.adr))
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self.comb += _addr.eq(wishbone.adr - base_address//4)
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# FSM.
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self.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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NextValue(_cmd_done, 0),
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