FIXED: the problem was that the write-side mux polarity is flipped

went through and checked the written values in memory, and it
looks like I had them flipped. This should fix that.

More testing is needed, but at this point I think a pretty rich
set of corner cases have been hit from my test bench perspective.

Not sure what the status of this RFC should be -- the Upconverter
doesn't work as-is for AXI, mainly because you're allowed to
initiate writes at unaligned addresses from what the converter
expects, but the converter was oblivious to addresses.

The changes I've made bring the address data into the converter
so it can setup the mux appropriately.

Only tested for 32->64 bit conversions, which is the case of
interest for me, but, I'll update this if I find any more corner
cases.

litex/soc/interconnect/stream.py

@@ -380,7 +380,7 @@ class _UpConverter(Module):
             If(source.ready, strobe_all.eq(0)),
             If(load_addr,
                 If(prime_demux,
-                    demux_val.eq( (self.aw & 7) > 3 ),
+                    demux_val.eq( (self.aw & 7) < 4 ),
                 ).Else(
                     demux_val.eq(demux_val + 1),
                 ),
@@ -453,7 +453,7 @@ class _DownConverter(Module):
         # Data path
         cases = {}
         for i in range(ratio):
-            n = ratio-i-1 if not reverse else i # FIXME: flipped polarity for AXI stream case. Need to figure out how to make more generic?
+            n = ratio-i-1 if reverse else i
             cases[i] = source.data.eq(sink.data[n*nbits_to:(n+1)*nbits_to])
         self.comb += Case(mux, cases).makedefault()