Use new ClockDomain API
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2
build.py
2
build.py
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@ -60,7 +60,7 @@ NET "asfifo*/preset_empty*" TIG;
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"jtag_tap_spartan6.v", "lm32_itlb.v", "lm32_dtlb.v")
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"jtag_tap_spartan6.v", "lm32_itlb.v", "lm32_dtlb.v")
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plat.add_sources(os.path.join("verilog", "lm32"), "lm32_config.v")
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plat.add_sources(os.path.join("verilog", "lm32"), "lm32_config.v")
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plat.build_cmdline(soc, clock_domains=soc.crg.get_clock_domains())
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plat.build_cmdline(soc)
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if __name__ == "__main__":
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if __name__ == "__main__":
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main()
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main()
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@ -3,9 +3,8 @@ from fractions import Fraction
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from migen.fhdl.structure import *
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from migen.fhdl.structure import *
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from migen.fhdl.specials import Instance
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from migen.fhdl.specials import Instance
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from migen.fhdl.module import Module
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from migen.fhdl.module import Module
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from mibuild.crg import CRG
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class M1CRG(Module, CRG):
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class M1CRG(Module):
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def __init__(self, infreq, outfreq1x):
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def __init__(self, infreq, outfreq1x):
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self.clk50_pad = Signal()
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self.clk50_pad = Signal()
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self.trigger_reset = Signal()
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self.trigger_reset = Signal()
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@ -13,13 +12,13 @@ class M1CRG(Module, CRG):
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self.eth_rx_clk_pad = Signal()
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self.eth_rx_clk_pad = Signal()
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self.eth_tx_clk_pad = Signal()
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self.eth_tx_clk_pad = Signal()
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self.cd_sys = ClockDomain("sys")
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self.clock_domains.cd_sys = ClockDomain()
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self.cd_sys2x_270 = ClockDomain("sys2x_270")
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self.clock_domains.cd_sys2x_270 = ClockDomain()
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self.cd_sys4x_wr = ClockDomain("sys4x_wr")
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self.clock_domains.cd_sys4x_wr = ClockDomain()
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self.cd_sys4x_rd = ClockDomain("sys4x_rd")
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self.clock_domains.cd_sys4x_rd = ClockDomain()
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self.cd_eth_rx = ClockDomain("eth_rx")
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self.clock_domains.cd_eth_rx = ClockDomain()
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self.cd_eth_tx = ClockDomain("eth_tx")
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self.clock_domains.cd_eth_tx = ClockDomain()
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self.cd_vga = ClockDomain("vga")
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self.clock_domains.cd_vga = ClockDomain()
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ratio = Fraction(outfreq1x)/Fraction(infreq)
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ratio = Fraction(outfreq1x)/Fraction(infreq)
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in_period = float(Fraction(1000000000)/Fraction(infreq))
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in_period = float(Fraction(1000000000)/Fraction(infreq))
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