build/xilinx/vivado: improve readability of generated tcl/xdc files
This commit is contained in:
Florent Kermarrec
parent
7bc34a9bc7
commit
b22ad1acfb
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@ -1,4 +1,4 @@
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# This file is Copyright (c) 2014-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# This file is Copyright (c) 2014-2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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import os
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@ -15,6 +15,12 @@ from litex.build.xilinx import common
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# Constraints (.xdc) -------------------------------------------------------------------------------
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def _xdc_separator(msg):
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r = "#"*80 + "\n"
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r += "# " + msg + "\n"
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r += "#"*80 + "\n"
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return r
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def _format_xdc_constraint(c):
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if isinstance(c, Pins):
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return "set_property LOC " + c.identifiers[0]
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@ -35,15 +41,16 @@ def _format_xdc(signame, resname, *constraints):
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fmt_r = resname[0] + ":" + str(resname[1])
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if resname[2] is not None:
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fmt_r += "." + resname[2]
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r = " ## {}\n".format(fmt_r)
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r = "# {}\n".format(fmt_r)
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for c in fmt_c:
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if c is not None:
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r += c + " [get_ports " + signame + "]\n"
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r += "\n"
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return r
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def _build_xdc(named_sc, named_pc):
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r = ""
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r = _xdc_separator("IO constraints")
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for sig, pins, others, resname in named_sc:
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if len(pins) > 1:
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for i, p in enumerate(pins):
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@ -52,6 +59,7 @@ def _build_xdc(named_sc, named_pc):
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r += _format_xdc(sig, resname, Pins(pins[0]), *others)
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else:
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r += _format_xdc(sig, resname, *others)
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r += _xdc_separator("Design constraints")
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if named_pc:
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r += "\n" + "\n\n".join(named_pc)
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return r
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@ -130,15 +138,18 @@ class XilinxVivadoToolchain:
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tcl = []
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# Create project
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tcl.append("\n# Create Project\n")
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tcl.append("create_project -force -name {} -part {}".format(build_name, platform.device))
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tcl.append("set_msg_config -id {Common 17-55} -new_severity {Warning}")
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# Enable Xilinx Parameterized Macros
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if enable_xpm:
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tcl.append("\n# Enable Xilinx Parameterized Macros\n")
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tcl.append("set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project]")
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# Add sources (when Vivado used for synthesis)
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if synth_mode == "vivado":
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tcl.append("\n# Add Sources\n")
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# "-include_dirs {}" crashes Vivado 2016.4
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for filename, language, library in platform.sources:
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filename_tcl = "{" + filename + "}"
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@ -154,11 +165,13 @@ class XilinxVivadoToolchain:
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tcl.append("add_files " + filename_tcl)
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# Add EDIFs
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tcl.append("\n# Add EDIFs\n")
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for filename in platform.edifs:
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filename_tcl = "{" + filename + "}"
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tcl.append("read_edif " + filename_tcl)
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# Add Ips
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# Add IPs
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tcl.append("\n# Add IPs\n")
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for filename in platform.ips:
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filename_tcl = "{" + filename + "}"
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ip = os.path.splitext(os.path.basename(filename))[0]
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@ -169,39 +182,51 @@ class XilinxVivadoToolchain:
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tcl.append("get_files -all -of_objects [get_files {}]".format(filename_tcl))
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# Add constraints
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tcl.append("\n# Add constraints\n")
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tcl.append("read_xdc {}.xdc".format(build_name))
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# Add pre-synthesis commands
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tcl.append("\n# Add pre-synthesis commands\n")
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tcl.extend(c.format(build_name=build_name) for c in self.pre_synthesis_commands)
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# Synthesis
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if synth_mode == "vivado":
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tcl.append("\n# Synthesis\n")
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synth_cmd = "synth_design -directive {} -top {} -part {}".format(self.vivado_synth_directive,
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build_name, platform.device)
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if platform.verilog_include_paths:
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synth_cmd += " -include_dirs {{{}}}".format(" ".join(platform.verilog_include_paths))
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tcl.append(synth_cmd)
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elif synth_mode == "yosys":
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tcl.append("\n# Read Yosys EDIF\n")
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tcl.append("read_edif {}.edif".format(build_name))
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tcl.append("link_design -top {} -part {}".format(build_name, platform.device))
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else:
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raise OSError("Unknown synthesis mode! {}".format(synth_mode))
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tcl.append("\n# Synthesis report\n")
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tcl.append("report_timing_summary -file {}_timing_synth.rpt".format(build_name))
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tcl.append("report_utilization -hierarchical -file {}_utilization_hierarchical_synth.rpt".format(build_name))
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tcl.append("report_utilization -file {}_utilization_synth.rpt".format(build_name))
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# Optimize
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tcl.append("\n# Optimize design\n")
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tcl.append("opt_design -directive {}".format(self.opt_directive))
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# Incremental implementation
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if self.incremental_implementation:
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tcl.append("\n# Read design checkpoint\n")
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tcl.append("read_checkpoint -incremental {}_route.dcp".format(build_name))
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# Add pre-placement commands
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tcl.append("\n# Add pre-placement commands\n")
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tcl.extend(c.format(build_name=build_name) for c in self.pre_placement_commands)
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# Placement
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tcl.append("\n# Placement\n")
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tcl.append("place_design -directive {}".format(self.vivado_place_directive))
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if self.vivado_post_place_phys_opt_directive:
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tcl.append("phys_opt_design -directive {}".format(self.vivado_post_place_phys_opt_directive))
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tcl.append("\n# Placement report\n")
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tcl.append("report_utilization -hierarchical -file {}_utilization_hierarchical_place.rpt".format(build_name))
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tcl.append("report_utilization -file {}_utilization_place.rpt".format(build_name))
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tcl.append("report_io -file {}_io.rpt".format(build_name))
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@ -209,13 +234,16 @@ class XilinxVivadoToolchain:
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tcl.append("report_clock_utilization -file {}_clock_utilization.rpt".format(build_name))
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# Add pre-routing commands
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tcl.append("\n# Add pre-routing commands\n")
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tcl.extend(c.format(build_name=build_name) for c in self.pre_routing_commands)
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# Routing
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tcl.append("\n# Routing\n")
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tcl.append("route_design -directive {}".format(self.vivado_route_directive))
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tcl.append("phys_opt_design -directive {}".format(self.vivado_post_route_phys_opt_directive))
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tcl.append("report_timing_summary -no_header -no_detailed_paths")
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tcl.append("write_checkpoint -force {}_route.dcp".format(build_name))
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tcl.append("\n# Routing report\n")
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tcl.append("report_timing_summary -no_header -no_detailed_paths")
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tcl.append("report_route_status -file {}_route_status.rpt".format(build_name))
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tcl.append("report_drc -file {}_drc.rpt".format(build_name))
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tcl.append("report_timing_summary -datasheet -max_paths 10 -file {}_timing.rpt".format(build_name))
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@ -224,15 +252,18 @@ class XilinxVivadoToolchain:
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tcl.append(bitstream_command.format(build_name=build_name))
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# Bitstream generation
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tcl.append("\n# Bitstream generation\n")
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tcl.append("write_bitstream -force {}.bit ".format(build_name))
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for additional_command in self.additional_commands:
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tcl.append(additional_command.format(build_name=build_name))
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# Quit
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tcl.append("\n# End\n")
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tcl.append("quit")
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tools.write_to_file(build_name + ".tcl", "\n".join(tcl))
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def _build_clock_constraints(self, platform):
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platform.add_platform_command(_xdc_separator("Clock constraints"))
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for clk, period in sorted(self.clocks.items(), key=lambda x: x[0].duid):
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platform.add_platform_command(
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"create_clock -name {clk} -period " + str(period) +
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@ -250,6 +281,7 @@ class XilinxVivadoToolchain:
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del self.false_paths
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def _build_false_path_constraints(self, platform):
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platform.add_platform_command(_xdc_separator("False path constraints"))
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# The asynchronous input to a MultiReg is a false path
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platform.add_platform_command(
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"set_false_path -quiet "
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