Add an hacked no we memory for Efinix
Efinity synthesizer cannot infer RAM blocks with write enable. In order to workaround this (at least for the Litex SoC intergrated RAM/ROM) a dirty modified Memory class has been created. This class needs to be rewrite !
This commit is contained in:
Franck Jullien
parent
bd71dc663f
commit
b24475b07d
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@ -0,0 +1,175 @@
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from migen.fhdl.structure import *
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from migen.fhdl.module import *
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from migen.fhdl.bitcontainer import bits_for
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from migen.fhdl.tools import *
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from migen.fhdl.tracer import get_obj_var_name
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from migen.fhdl.verilog import _printexpr as verilog_printexpr
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from migen.fhdl.specials import Special, _MemoryPort, _MemoryLocation
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(READ_FIRST, WRITE_FIRST, NO_CHANGE) = range(3)
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class Memory(Special):
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def __init__(self, width, depth, init=None, name=None):
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Special.__init__(self)
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self.width = width
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self.depth = depth
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self.ports = []
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self.init = init
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self.name_override = get_obj_var_name(name, "mem")
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def __getitem__(self, index):
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# simulation only
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return _MemoryLocation(self, index)
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def get_port(self, write_capable=False, async_read=False,
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has_re=False, we_granularity=0, mode=WRITE_FIRST,
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clock_domain="sys"):
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if we_granularity >= self.width:
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we_granularity = 0
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adr = Signal(max=self.depth)
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dat_r = Signal(self.width)
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if write_capable:
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if we_granularity:
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we = Signal(self.width//we_granularity)
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else:
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we = Signal()
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dat_w = Signal(self.width)
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else:
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we = None
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dat_w = None
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if has_re:
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re = Signal()
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else:
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re = None
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mp = _MemoryPort(adr, dat_r, we, dat_w,
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async_read, re, we_granularity, mode,
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clock_domain)
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self.ports.append(mp)
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return mp
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@staticmethod
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def emit_verilog(memory, ns, add_data_file):
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r = ""
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def gn(e):
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if isinstance(e, Memory):
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return ns.get_name(e)
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else:
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return verilog_printexpr(ns, e)[0]
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adrbits = bits_for(memory.depth-1)
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for i in range(memory.width // 8):
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r += "reg [" + str((memory.width//4)-1) + ":0] " \
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+ gn(memory) + '_' + str(i) \
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+ "[0:" + str(memory.depth-1) + "];\n"
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adr_regs = {}
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data_regs = {}
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for port in memory.ports:
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if not port.async_read:
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if port.mode == WRITE_FIRST:
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adr_reg = Signal(name_override="memadr")
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r += "reg [" + str(adrbits-1) + ":0] " \
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+ gn(adr_reg) + ";\n"
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adr_regs[id(port)] = adr_reg
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else:
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data_reg = Signal(name_override="memdat")
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r += "reg [" + str(memory.width-1) + ":0] " \
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+ gn(data_reg) + ";\n"
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data_regs[id(port)] = data_reg
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for port in memory.ports:
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r += "always @(posedge " + gn(port.clock) + ") begin\n"
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if port.we is not None:
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if port.we_granularity:
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n = memory.width//port.we_granularity
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for i in range(n):
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if (i > 0):
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r += "always @(posedge " + gn(port.clock) + ") begin\n"
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m = i*port.we_granularity
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M = (i+1)*port.we_granularity-1
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sl = "[" + str(M) + ":" + str(m) + "]"
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r += "\tif (" + gn(port.we) + "[" + str(i) + "])\n"
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r += "\t\t" + gn(memory) + '_' + str(i) + "[" + gn(port.adr) + "]" + " <= " + gn(port.dat_w) + sl + ";\n"
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r += "end\n"
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else:
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r += "\tif (" + gn(port.we) + ")\n"
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r += "\t\t" + gn(memory) + "[" + gn(port.adr) + "] <= " + gn(port.dat_w) + ";\n"
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if not port.async_read:
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if port.mode == WRITE_FIRST:
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r += "always @(posedge " + gn(port.clock) + ") begin\n"
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rd = "\t" + gn(adr_regs[id(port)]) + " <= " + gn(port.adr) + ";\n"
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else:
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bassign = ""
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for i in range(memory.width // 8):
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m = i*port.we_granularity
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M = (i+1)*port.we_granularity-1
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sl = "[" + str(M) + ":" + str(m) + "]"
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bassign += gn(data_regs[id(port)]) + sl + " <= " + gn(memory) + "_" + str(i) + "[" + gn(port.adr) + "];\n"
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if port.mode == READ_FIRST:
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rd = "\t" + bassign
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elif port.mode == NO_CHANGE:
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rd = "\tif (!" + gn(port.we) + ")\n" \
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+ "\t\t" + bassign
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if port.re is None:
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r += rd
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else:
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r += "\tif (" + gn(port.re) + ")\n"
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r += "\t" + rd.replace("\n\t", "\n\t\t")
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r += "end\n\n"
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for port in memory.ports:
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if port.async_read:
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r += "assign " + gn(port.dat_r) + " = " + gn(memory) + "[" + gn(port.adr) + "];\n"
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else:
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if port.mode == WRITE_FIRST:
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for i in range(memory.width // 8):
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m = i*port.we_granularity
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M = (i+1)*port.we_granularity-1
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sl = "[" + str(M) + ":" + str(m) + "]"
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r += "assign " + gn(port.dat_r) + sl + " = " + gn(memory) + "_" + str(i) + "[" + gn(adr_regs[id(port)]) + "];\n"
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else:
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r += "assign " + gn(port.dat_r) + " = " + gn(data_regs[id(port)]) + ";\n"
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r += "\n"
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if memory.init is not None:
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content_7_0 = ""
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content_15_8 = ""
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content_23_16 = ""
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content_31_24 = ""
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formatter = "{:0" + str(int(memory.width / 4)) + "X}\n"
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init_7_0 = []
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init_15_8 = []
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init_23_16 = []
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init_31_24 = []
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for w in memory.init:
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init_7_0.append(w & 0xff)
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init_15_8.append((w >> 8) & 0xff)
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init_23_16.append((w >> 16) & 0xff)
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init_31_24.append((w >> 24) & 0xff)
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for d in init_7_0:
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content_7_0 += formatter.format(d)
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for d in init_15_8:
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content_15_8 += formatter.format(d)
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for d in init_23_16:
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content_23_16 += formatter.format(d)
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for d in init_31_24:
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content_31_24 += formatter.format(d)
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memory_filename1 = add_data_file(gn(memory) + "1.init", content_7_0)
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memory_filename2 = add_data_file(gn(memory) + "2.init", content_15_8)
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memory_filename3 = add_data_file(gn(memory) + "3.init", content_23_16)
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memory_filename4 = add_data_file(gn(memory) + "4.init", content_31_24)
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r += "initial begin\n"
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r += "\t$readmemh(\"" + memory_filename1 + "\", " + gn(memory)+ "_0" + ");\n"
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r += "\t$readmemh(\"" + memory_filename2 + "\", " + gn(memory)+ "_1" + ");\n"
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r += "\t$readmemh(\"" + memory_filename3 + "\", " + gn(memory)+ "_2" + ");\n"
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r += "\t$readmemh(\"" + memory_filename4 + "\", " + gn(memory)+ "_3" + ");\n"
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r += "end\n\n"
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return r
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@ -815,7 +815,7 @@ class SoC(Module):
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self.check_if_exists(name)
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setattr(self.submodules, name, SoCController(**kwargs))
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def add_ram(self, name, origin, size, contents=[], mode="rw"):
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def add_ram(self, name, origin, size, contents=[], mode="rw", no_we=False):
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ram_cls = {
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"wishbone": wishbone.SRAM,
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"axi-lite": axi.AXILiteSRAM,
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@ -825,7 +825,7 @@ class SoC(Module):
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"axi-lite": axi.AXILiteInterface,
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}[self.bus.standard]
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ram_bus = interface_cls(data_width=self.bus.data_width)
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ram = ram_cls(size, bus=ram_bus, init=contents, read_only=(mode == "r"))
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ram = ram_cls(size, bus=ram_bus, init=contents, read_only=(mode == "r"), no_we=no_we)
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self.bus.add_slave(name, ram.bus, SoCRegion(origin=origin, size=size, mode=mode))
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self.check_if_exists(name)
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self.logger.info("RAM {} {} {}.".format(
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@ -834,8 +834,8 @@ class SoC(Module):
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self.bus.regions[name]))
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setattr(self.submodules, name, ram)
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def add_rom(self, name, origin, size, contents=[], mode="r"):
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self.add_ram(name, origin, size, contents, mode=mode)
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def add_rom(self, name, origin, size, contents=[], mode="r", no_we=False):
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self.add_ram(name, origin, size, contents, mode=mode, no_we=no_we)
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def init_rom(self, name, contents=[], auto_size=True):
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self.logger.info("Initializing ROM {} with contents (Size: {}).".format(
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@ -79,10 +79,12 @@ class SoCCore(LiteXSoC):
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integrated_rom_size = 0,
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integrated_rom_mode = "r",
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integrated_rom_init = [],
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integrated_rom_no_we = False,
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# SRAM parameters
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integrated_sram_size = 0x2000,
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integrated_sram_init = [],
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integrated_sram_no_we = False,
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# MAIN_RAM parameters
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integrated_main_ram_size = 0,
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@ -197,11 +199,11 @@ class SoCCore(LiteXSoC):
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# Add integrated ROM
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if integrated_rom_size:
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self.add_rom("rom", self.cpu.reset_address, integrated_rom_size, integrated_rom_init, integrated_rom_mode)
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self.add_rom("rom", self.cpu.reset_address, integrated_rom_size, integrated_rom_init, integrated_rom_mode, no_we=integrated_rom_no_we)
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# Add integrated SRAM
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if integrated_sram_size:
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self.add_ram("sram", self.mem_map["sram"], integrated_sram_size)
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self.add_ram("sram", self.mem_map["sram"], integrated_sram_size, no_we=integrated_sram_no_we)
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# Add integrated MAIN_RAM (only useful when no external SRAM/SDRAM is available)
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if integrated_main_ram_size:
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@ -783,7 +783,7 @@ class AXILite2CSR(Module):
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# AXILite SRAM -------------------------------------------------------------------------------------
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class AXILiteSRAM(Module):
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def __init__(self, mem_or_size, read_only=None, init=None, bus=None):
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def __init__(self, mem_or_size, read_only=None, init=None, bus=None, no_we=False):
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if bus is None:
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bus = AXILiteInterface()
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self.bus = bus
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@ -329,7 +329,7 @@ class Converter(Module):
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# Wishbone SRAM ------------------------------------------------------------------------------------
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class SRAM(Module):
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def __init__(self, mem_or_size, read_only=None, init=None, bus=None):
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def __init__(self, mem_or_size, read_only=None, init=None, bus=None, no_we=False):
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if bus is None:
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bus = Interface()
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self.bus = bus
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@ -337,8 +337,13 @@ class SRAM(Module):
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if isinstance(mem_or_size, Memory):
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assert(mem_or_size.width <= bus_data_width)
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self.mem = mem_or_size
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else:
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if no_we:
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from litex.gen.fhdl.memory import Memory as NoWeMemory
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self.mem = NoWeMemory(bus_data_width, mem_or_size//(bus_data_width//8), init=init)
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else:
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self.mem = Memory(bus_data_width, mem_or_size//(bus_data_width//8), init=init)
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if read_only is None:
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if hasattr(self.mem, "bus_read_only"):
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read_only = self.mem.bus_read_only
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