soc/cores/jtag: Review/Cleanup JTAGTAPFSM and avoid specific CorrectedOngoingResetFSM.
This commit is contained in:
Florent Kermarrec
parent
40799332a0
commit
b2448ba50e
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@ -1,37 +0,0 @@
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#
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# This file is part of LiteX.
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#
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# Copyright (c) 2021 Jevin Sweval <jevinsweval@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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from collections import OrderedDict
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from migen.genlib.fsm import FSM
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class CorrectedOngoingResetFSM(FSM):
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"""
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This wrapper is needed for FSMs where an ongoing signal from the FSM's reset state is used.
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With the existing FSM, on SoC reset the FSM will be in the reset state
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but its ongoing signal will not be asserted because the existing FSM
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does not set the reset values of the ongoing signals.
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"""
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def __init__(self, *args, **kwargs):
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super().__init__(*args, **kwargs)
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self.ongoing_signals = OrderedDict()
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def ongoing(self, state, *args, **kwargs):
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is_ongoing = super().ongoing(state, *args, **kwargs)
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self.ongoing_signals[state] = is_ongoing
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return is_ongoing
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def do_finalize(self, *args, **kwargs):
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for state, is_ongoing in self.ongoing_signals.items():
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is_ongoing.reset = 1 if state == self.reset_state else 0
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if is_ongoing.reset.value:
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# since the default is high, must explicitly deassert in all other states
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for other_state in set(self.actions) - set([state]):
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self.actions[other_state].append(is_ongoing.eq(0))
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super().do_finalize(*args, **kwargs)
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@ -1,7 +1,7 @@
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#
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# This file is part of LiteX.
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#
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# Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2019-2022 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2019 Antti Lukats <antti.lukats@gmail.com>
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# Copyright (c) 2017 Robert Jordens <jordens@gmail.com>
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# Copyright (c) 2021 Gregory Davill <greg.davill@gmail.com>
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@ -18,70 +18,143 @@ from litex.soc.interconnect import stream
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# JTAG TAP FSM -------------------------------------------------------------------------------------
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class JTAGTAPFSM(Module):
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def __init__(self, tms: Signal, tck: Signal, expose_signals=True):
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self.submodules.fsm = fsm = ClockDomainsRenamer("jtag")(CorrectedOngoingResetFSM())
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def __init__(self, tms):
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self.submodules.fsm = fsm = FSM(reset_state="TEST_LOGIC_RESET")
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fsm.act("test_logic_reset",
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If(~tms, NextState("run_test_idle"))
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)
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fsm.act("run_test_idle",
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If( tms, NextState("select_dr_scan"))
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def JTAGTAPFSMState(name, transitions={}):
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logic = []
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# Transitions logic.
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nextstates = {}
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nextstates[0] = NextState(transitions.get(0, name))
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nextstates[1] = NextState(transitions.get(1, name))
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logic.append(Case(tms, nextstates))
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# Ongoing logic.
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ongoing = Signal()
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setattr(self, name, ongoing)
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logic.append(ongoing.eq(1))
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# Add logic to state.
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fsm.act(name, *logic)
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# Test-Logic-Reset.
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# -----------------
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JTAGTAPFSMState(
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name = "TEST_LOGIC_RESET",
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transitions = {
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0 : "RUN_TEST_IDLE",
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}
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)
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# DR
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fsm.act("select_dr_scan",
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If(~tms, NextState("capture_dr") ).Else(NextState("select_ir_scan"))
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)
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fsm.act("capture_dr",
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If(~tms, NextState("shift_dr") ).Else(NextState("exit1_dr"))
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)
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fsm.act("shift_dr",
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If( tms, NextState("exit1_dr"))
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)
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fsm.act("exit1_dr",
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If(~tms, NextState("pause_dr") ).Else(NextState("update_dr"))
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)
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fsm.act("pause_dr",
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If( tms, NextState("exit2_dr"))
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)
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fsm.act("exit2_dr",
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If( tms, NextState("update_dr") ).Else(NextState("shift_dr"))
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)
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fsm.act("update_dr",
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If( tms, NextState("select_dr_scan")).Else(NextState("run_test_idle"))
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# Run-Test/Idle.
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# --------------
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JTAGTAPFSMState(
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name = "RUN_TEST_IDLE",
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transitions = {
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1 : "SELECT_DR_SCAN",
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}
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)
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# IR
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fsm.act("select_ir_scan",
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If(~tms, NextState("capture_ir") ).Else(NextState("test_logic_reset"))
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# DR-Scan.
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# --------
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JTAGTAPFSMState(
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name = "SELECT_DR_SCAN",
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transitions = {
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0 : "CAPTURE_DR",
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1 : "SELECT_IR_SCAN",
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}
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)
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fsm.act("capture_ir",
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If(~tms, NextState("shift_ir") ).Else(NextState("exit1_ir"))
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JTAGTAPFSMState(
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name = "CAPTURE_DR",
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transitions = {
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0 : "SHIFT_DR",
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1 : "EXIT1_DR",
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}
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)
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fsm.act("shift_ir",
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If( tms, NextState("exit1_ir"))
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JTAGTAPFSMState(
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name = "SHIFT_DR",
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transitions = {
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1 : "EXIT1_DR",
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}
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)
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fsm.act("exit1_ir",
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If(~tms, NextState("pause_ir") ).Else(NextState("update_ir"))
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JTAGTAPFSMState(
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name = "EXIT1_DR",
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transitions = {
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0 : "PAUSE_DR",
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1 : "UPDATE_DR",
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}
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)
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fsm.act("pause_ir",
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If( tms, NextState("exit2_ir"))
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JTAGTAPFSMState(
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name = "PAUSE_DR",
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transitions = {
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1 : "EXIT2_DR",
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}
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)
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fsm.act("exit2_ir",
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If( tms, NextState("update_ir") ).Else(NextState("shift_ir"))
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JTAGTAPFSMState(
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name = "EXIT2_DR",
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transitions = {
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0 : "SHIFT_DR",
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1 : "UPDATE_DR",
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}
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)
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fsm.act("update_ir",
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If( tms, NextState("select_dr_scan")).Else(NextState("run_test_idle"))
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JTAGTAPFSMState(
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name = "UPDATE_DR",
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transitions = {
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0 : "RUN_TEST_IDLE",
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1 : "SELECT_DR_SCAN",
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}
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)
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if expose_signals:
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for state_name in fsm.actions:
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state_sig = fsm.ongoing(state_name)
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SHOUTING_NAME = state_name.upper()
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shouting_sig = Signal(name=SHOUTING_NAME)
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setattr(self, SHOUTING_NAME, shouting_sig)
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self.comb += shouting_sig.eq(state_sig)
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# IR-Scan.
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# --------
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JTAGTAPFSMState(
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name = "SELECT_IR_SCAN",
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transitions = {
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0 : "CAPTURE_IR",
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1 : "TEST_LOGIC_RESET",
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}
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)
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JTAGTAPFSMState(
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name = "CAPTURE_IR",
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transitions = {
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0 : "SHIFT_IR",
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1 : "EXIT1_IR",
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}
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)
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JTAGTAPFSMState(
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name = "SHIFT_IR",
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transitions = {
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1 : "EXIT1_IR",
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}
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)
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JTAGTAPFSMState(
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name = "EXIT1_IR",
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transitions = {
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0 : "PAUSE_IR",
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1 : "UPDATE_IR",
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}
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)
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JTAGTAPFSMState(
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name = "PAUSE_IR",
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transitions = {
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1 : "EXIT2_IR",
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}
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)
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JTAGTAPFSMState(
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name = "EXIT2_IR",
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transitions = {
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0 : "SHIFT_IR",
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1 : "UPDATE_IR",
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}
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)
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JTAGTAPFSMState(
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name = "UPDATE_IR",
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transitions = {
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0 : "RUN_TEST_IDLE",
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1 : "SELECT_DR_SCAN",
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}
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)
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# Altera JTAG --------------------------------------------------------------------------------------
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@ -124,7 +197,7 @@ class AlteraJTAG(Module):
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self.comb += ResetSignal("jtag_inv").eq(ResetSignal("jtag"))
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# connect the TAP state signals that LiteX expects but the HW IP doesn't provide
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self.submodules.tap_fsm = JTAGTAPFSM(tms, tck)
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self.submodules.tap_fsm = ClockDomainsRenamer("jtag")(JTAGTAPFSM(tms))
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self.sync.jtag_inv += reset.eq(self.tap_fsm.TEST_LOGIC_RESET)
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self.sync.jtag_inv += capture.eq(self.tap_fsm.CAPTURE_DR)
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