cores/dna: Rewrite/simplify core and use a slower clock (sys_clk/16).

litex/soc/cores/dna.py

@@ -2,6 +2,7 @@
 # This file is part of LiteX.
 #
 # Copyright (c) 2014-2015 Robert Jordens <jordens@gmail.com>
+# Copyright (c) 2022 Florent Kermarrec <florent@enjoy-digital.fr>
 # SPDX-License-Identifier: BSD-2-Clause
 
 from migen import *
@@ -12,34 +13,36 @@ from litex.soc.interconnect.csr import *
 # Xilinx DNA (Device Identifier) -------------------------------------------------------------------
 
 class DNA(Module, AutoCSR):
+    nbits = 57
     def __init__(self):
-        n = 57
-        self._id = CSRStatus(n)
+        self._id = CSRStatus(self.nbits)
 
         # # #
 
-        self.do    = do    = Signal()
-        self.count = count = Signal(max=2*n + 1)
-        self.clk   = clk   = Signal()
+        # Create slow DNA Clk (sys_clk/16).
+        self.clock_domains.cd_dna = ClockDomain()
+        dna_clk_count = Signal(4)
+        self.sync += dna_clk_count.eq(dna_clk_count + 1)
+        self.sync += self.cd_dna.clk.eq(dna_clk_count[3])
 
-        self.comb += clk.eq(count[0])
+
+        # Shift-Out DNA Identifier.
+        count = Signal(8)
+        dout  = Signal()
         self.specials += Instance("DNA_PORT",
-                i_DIN   = self._id.status[-1],
-                o_DOUT  = do,
-                i_CLK   = clk,
-                i_READ  = count < 2,
-                i_SHIFT = 1
+            i_CLK   = ClockSignal("icap"),
+            i_READ  = (count == 0),
+            i_SHIFT = 1,
+            i_DIN   = 0,
+            o_DOUT  = dout,
         )
-
-        self.sync += [
-            If(count < 2*n,
+        self.sync.dna += [
+            If(count < (self.nbits + 1),
                 count.eq(count + 1),
-                If(clk,
-                    self._id.status.eq(Cat(do, self._id.status))
-                )
+                self._id.status.eq(Cat(dout, self._id.status))
             )
         ]
 
     def add_timing_constraints(self, platform, sys_clk_freq, sys_clk):
-        platform.add_period_constraint(self.clk, 2*1e9/sys_clk_freq)
-        platform.add_false_path_constraints(self.clk, sys_clk)
+        platform.add_period_constraint(self.cd_dna.clk, 16*1e9/sys_clk_freq)
+        platform.add_false_path_constraints(self.cd_dna.clk, sys_clk)