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merge litescope

This commit is contained in:
Florent Kermarrec 2015-02-28 10:24:49 +01:00
parent a43c555ee3 a559fc77c8
commit b274e948dc
75 changed files with 5611 additions and 0 deletions
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__pycache__
*.pyc
*.vcd

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Unless otherwise noted, LiteScope is copyright (C) 2015 Florent Kermarrec.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Other authors retain ownership of their contributions. If a submission can
reasonably be considered independently copyrightable, it's yours and we
encourage you to claim it with appropriate copyright notices. This submission
then falls under the "otherwise noted" category. All submissions are strongly
encouraged to use the two-clause BSD license reproduced above.

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__ _ __ ____
/ / (_) /____ / __/______ ___ ___
/ /__/ / __/ -_)\ \/ __/ _ \/ _ \/ -_)
/____/_/\__/\__/___/\__/\___/ .__/\__/
/_/
Copyright 2012-2015 / EnjoyDigital
florent@enjoy-digital.fr
A small footprint and configurable embedded FPGA
logic analyzer core powered by Migen
[> Doc
---------
HTML : www.enjoy-digital.fr/litex/litescope/
PDF : www.enjoy-digital.fr/litex/litescope.pdf
[> Intro
---------
LiteScope is a small footprint and configurable embedded logic analyzer that you
can use in your FPGA and aims to provide a free, portable and flexible
alternative to vendor's solutions!
LiteScope is part of LiteX libraries whose aims are to lower entry level of complex
FPGA cores by providing simple, elegant and efficient implementations of
components used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...
The core uses simple and specific streaming buses and will provides in the future
adapters to use standardized AXI or Avalon-ST streaming buses.
Since Python is used to describe the HDL, the core is highly and easily
configurable.
LiteScope uses technologies developed in partnership with M-Labs Ltd:
- Migen enables generating HDL with Python in an efficient way.
- MiSoC provides the basic blocks to build a powerful and small footprint SoC.
LiteScope can be used as a Migen/MiSoC library (by simply installing it
with the provided setup.py) or can be integrated with your standard design flow
by generating the verilog rtl that you will use as a standard core.
LiteScope produces "vcd" files that can be read in your regular waveforms viewer.
Since LiteScope also provides a UART <--> Wishbone brige so you only need 2
external Rx/Tx pins to be ready to debug or control all your Wishbone peripherals!
[> Features
-----------
- IO peek and poke with LiteScopeIO
- Logic analyser with LiteScopeLA:
- Various triggering modules: Term, Range, Edge (add yours! :)
- Run Length Encoder to "compress" data and increase recording depth
- Subsampling
- Storage qualifier
- Data storage in block rams
- Bridges:
- UART2Wishbone
- Ethernet2Wishbone ("Etherbone")
[> Possible improvements
-------------------------
- add standardized interfaces (AXI, Avalon-ST)
- add protocols analyzers
- add signals injection/generation
- add storage in DRAM
- add storage in HDD with LiteSATA core (to be released soon!)
- add PCIe Wishbone bridge with LitePCIe (to be released soon!)
- ... See below Support and consulting :)
If you want to support these features, please contact us at florent [AT]
enjoy-digital.fr. You can also contact our partner on the public mailing list
devel [AT] lists.m-labs.hk.
[> Getting started
------------------
1. Install Python3 and your vendor's software
2. Obtain Migen and install it:
git clone https://github.com/m-labs/migen
cd migen
python3 setup.py install
cd ..
Note: in case you have issues with Migen, please retry
with our forks at:
https://github.com/enjoy-digital/migen
until new features are merged.
3. Obtain LiteScope and install it:
git clone https://github.com/enjoy-digital/litescope
4. Build and load test design:
python3 make.py -s [platform] all
Supported platforms are the ones already supported by Mibuild:
de0nano, m1, mixxeo, kc705, zedboard...
5. Test design:
go to ./test directory and run:
python3 test_io.py
python3 test_la.py
[> Simulations:
XXX convert simulations
[> Tests :
XXX convert tests
[> License
-----------
LiteScope is released under the very permissive two-clause BSD license. Under the
terms of this license, you are authorized to use LiteScope for closed-source
proprietary designs.
Even though we do not require you to do so, those things are awesome, so please
do them if possible:
- tell us that you are using LiteScope
- cite LiteScope in publications related to research it has helped
- send us feedback and suggestions for improvements
- send us bug reports when something goes wrong
- send us the modifications and improvements you have done to LiteScope.
[> Support and consulting
--------------------------
We love open-source hardware and like sharing our designs with others.
LiteScope is developed and maintained by EnjoyDigital.
If you would like to know more about LiteScope or if you are already a happy user
and would like to extend it for your needs, EnjoyDigital can provide standard
commercial support as well as consulting services.
So feel free to contact us, we'd love to work with you! (and eventually shorten
the list of the possible improvements :)
[> Contact
E-mail: florent [AT] enjoy-digital.fr

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*.diff
*.pyc
*~
*.bc
*.md
# Ignore generated files
build/

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# Makefile for Sphinx documentation
#
# You can set these variables from the command line.
SPHINXOPTS =
SPHINXBUILD = sphinx-build
PAPER =
BUILDDIR = build
# User-friendly check for sphinx-build
ifeq ($(shell which $(SPHINXBUILD) >/dev/null 2>&1; echo $$?), 1)
$(error The '$(SPHINXBUILD)' command was not found. Make sure you have Sphinx installed, then set the SPHINXBUILD environment variable to point to the full path of the '$(SPHINXBUILD)' executable. Alternatively you can add the directory with the executable to your PATH. If you don't have Sphinx installed, grab it from http://sphinx-doc.org/)
endif
# Internal variables.
PAPEROPT_a4 = -D latex_paper_size=a4
PAPEROPT_letter = -D latex_paper_size=letter
ALLSPHINXOPTS = -d $(BUILDDIR)/doctrees $(PAPEROPT_$(PAPER)) $(SPHINXOPTS) source
# the i18n builder cannot share the environment and doctrees with the others
I18NSPHINXOPTS = $(PAPEROPT_$(PAPER)) $(SPHINXOPTS) source
.PHONY: help clean html dirhtml singlehtml pickle json htmlhelp qthelp devhelp epub latex latexpdf text man changes linkcheck doctest gettext
help:
@echo "Please use \`make <target>' where <target> is one of"
@echo " html to make standalone HTML files"
@echo " dirhtml to make HTML files named index.html in directories"
@echo " singlehtml to make a single large HTML file"
@echo " pickle to make pickle files"
@echo " json to make JSON files"
@echo " htmlhelp to make HTML files and a HTML help project"
@echo " epub to make an epub"
@echo " latex to make LaTeX files, you can set PAPER=a4 or PAPER=letter"
@echo " latexpdf to make LaTeX files and run them through pdflatex"
@echo " latexpdfja to make LaTeX files and run them through platex/dvipdfmx"
@echo " text to make text files"
@echo " man to make manual pages"
@echo " texinfo to make Texinfo files"
@echo " info to make Texinfo files and run them through makeinfo"
@echo " gettext to make PO message catalogs"
@echo " changes to make an overview of all changed/added/deprecated items"
@echo " xml to make Docutils-native XML files"
@echo " pseudoxml to make pseudoxml-XML files for display purposes"
@echo " linkcheck to check all external links for integrity"
@echo " doctest to run all doctests embedded in the documentation (if enabled)"
clean:
rm -rf $(BUILDDIR)/*
html:
$(SPHINXBUILD) -b html $(ALLSPHINXOPTS) $(BUILDDIR)/html
@echo
@echo "Build finished. The HTML pages are in $(BUILDDIR)/html."
dirhtml:
$(SPHINXBUILD) -b dirhtml $(ALLSPHINXOPTS) $(BUILDDIR)/dirhtml
@echo
@echo "Build finished. The HTML pages are in $(BUILDDIR)/dirhtml."
singlehtml:
$(SPHINXBUILD) -b singlehtml $(ALLSPHINXOPTS) $(BUILDDIR)/singlehtml
@echo
@echo "Build finished. The HTML page is in $(BUILDDIR)/singlehtml."
pickle:
$(SPHINXBUILD) -b pickle $(ALLSPHINXOPTS) $(BUILDDIR)/pickle
@echo
@echo "Build finished; now you can process the pickle files."
json:
$(SPHINXBUILD) -b json $(ALLSPHINXOPTS) $(BUILDDIR)/json
@echo
@echo "Build finished; now you can process the JSON files."
htmlhelp:
$(SPHINXBUILD) -b htmlhelp $(ALLSPHINXOPTS) $(BUILDDIR)/htmlhelp
@echo
@echo "Build finished; now you can run HTML Help Workshop with the" \
".hhp project file in $(BUILDDIR)/htmlhelp."
epub:
$(SPHINXBUILD) -b epub $(ALLSPHINXOPTS) $(BUILDDIR)/epub
@echo
@echo "Build finished. The epub file is in $(BUILDDIR)/epub."
latex:
$(SPHINXBUILD) -b latex $(ALLSPHINXOPTS) $(BUILDDIR)/latex
@echo
@echo "Build finished; the LaTeX files are in $(BUILDDIR)/latex."
@echo "Run \`make' in that directory to run these through (pdf)latex" \
"(use \`make latexpdf' here to do that automatically)."
latexpdf:
$(SPHINXBUILD) -b latex $(ALLSPHINXOPTS) $(BUILDDIR)/latex
@echo "Running LaTeX files through pdflatex..."
$(MAKE) -C $(BUILDDIR)/latex all-pdf
@echo "pdflatex finished; the PDF files are in $(BUILDDIR)/latex."
latexpdfja:
$(SPHINXBUILD) -b latex $(ALLSPHINXOPTS) $(BUILDDIR)/latex
@echo "Running LaTeX files through platex and dvipdfmx..."
$(MAKE) -C $(BUILDDIR)/latex all-pdf-ja
@echo "pdflatex finished; the PDF files are in $(BUILDDIR)/latex."
text:
$(SPHINXBUILD) -b text $(ALLSPHINXOPTS) $(BUILDDIR)/text
@echo
@echo "Build finished. The text files are in $(BUILDDIR)/text."
man:
$(SPHINXBUILD) -b man $(ALLSPHINXOPTS) $(BUILDDIR)/man
@echo
@echo "Build finished. The manual pages are in $(BUILDDIR)/man."
texinfo:
$(SPHINXBUILD) -b texinfo $(ALLSPHINXOPTS) $(BUILDDIR)/texinfo
@echo
@echo "Build finished. The Texinfo files are in $(BUILDDIR)/texinfo."
@echo "Run \`make' in that directory to run these through makeinfo" \
"(use \`make info' here to do that automatically)."
info:
$(SPHINXBUILD) -b texinfo $(ALLSPHINXOPTS) $(BUILDDIR)/texinfo
@echo "Running Texinfo files through makeinfo..."
make -C $(BUILDDIR)/texinfo info
@echo "makeinfo finished; the Info files are in $(BUILDDIR)/texinfo."
gettext:
$(SPHINXBUILD) -b gettext $(I18NSPHINXOPTS) $(BUILDDIR)/locale
@echo
@echo "Build finished. The message catalogs are in $(BUILDDIR)/locale."
changes:
$(SPHINXBUILD) -b changes $(ALLSPHINXOPTS) $(BUILDDIR)/changes
@echo
@echo "The overview file is in $(BUILDDIR)/changes."
linkcheck:
$(SPHINXBUILD) -b linkcheck $(ALLSPHINXOPTS) $(BUILDDIR)/linkcheck
@echo
@echo "Link check complete; look for any errors in the above output " \
"or in $(BUILDDIR)/linkcheck/output.txt."
doctest:
$(SPHINXBUILD) -b doctest $(ALLSPHINXOPTS) $(BUILDDIR)/doctest
@echo "Testing of doctests in the sources finished, look at the " \
"results in $(BUILDDIR)/doctest/output.txt."
xml:
$(SPHINXBUILD) -b xml $(ALLSPHINXOPTS) $(BUILDDIR)/xml
@echo
@echo "Build finished. The XML files are in $(BUILDDIR)/xml."
pseudoxml:
$(SPHINXBUILD) -b pseudoxml $(ALLSPHINXOPTS) $(BUILDDIR)/pseudoxml
@echo
@echo "Build finished. The pseudo-XML files are in $(BUILDDIR)/pseudoxml."

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@ECHO OFF
REM Command file for Sphinx documentation
if "%SPHINXBUILD%" == "" (
set SPHINXBUILD=sphinx-build
)
set BUILDDIR=build
set ALLSPHINXOPTS=-d %BUILDDIR%/doctrees %SPHINXOPTS% source
set I18NSPHINXOPTS=%SPHINXOPTS% source
if NOT "%PAPER%" == "" (
set ALLSPHINXOPTS=-D latex_paper_size=%PAPER% %ALLSPHINXOPTS%
set I18NSPHINXOPTS=-D latex_paper_size=%PAPER% %I18NSPHINXOPTS%
)
if "%1" == "" goto help
if "%1" == "help" (
:help
echo.Please use `make ^<target^>` where ^<target^> is one of
echo. html to make standalone HTML files
echo. dirhtml to make HTML files named index.html in directories
echo. singlehtml to make a single large HTML file
echo. pickle to make pickle files
echo. json to make JSON files
echo. htmlhelp to make HTML files and a HTML help project
echo. epub to make an epub
echo. latex to make LaTeX files, you can set PAPER=a4 or PAPER=letter
echo. text to make text files
echo. man to make manual pages
echo. texinfo to make Texinfo files
echo. gettext to make PO message catalogs
echo. changes to make an overview over all changed/added/deprecated items
echo. xml to make Docutils-native XML files
echo. pseudoxml to make pseudoxml-XML files for display purposes
echo. linkcheck to check all external links for integrity
echo. doctest to run all doctests embedded in the documentation if enabled
goto end
)
if "%1" == "clean" (
for /d %%i in (%BUILDDIR%\*) do rmdir /q /s %%i
del /q /s %BUILDDIR%\*
goto end
)
%SPHINXBUILD% 2> nul
if errorlevel 9009 (
echo.
echo.The 'sphinx-build' command was not found. Make sure you have Sphinx
echo.installed, then set the SPHINXBUILD environment variable to point
echo.to the full path of the 'sphinx-build' executable. Alternatively you
echo.may add the Sphinx directory to PATH.
echo.
echo.If you don't have Sphinx installed, grab it from
echo.http://sphinx-doc.org/
exit /b 1
)
if "%1" == "html" (
%SPHINXBUILD% -b html %ALLSPHINXOPTS% %BUILDDIR%/html
if errorlevel 1 exit /b 1
echo.
echo.Build finished. The HTML pages are in %BUILDDIR%/html.
goto end
)
if "%1" == "dirhtml" (
%SPHINXBUILD% -b dirhtml %ALLSPHINXOPTS% %BUILDDIR%/dirhtml
if errorlevel 1 exit /b 1
echo.
echo.Build finished. The HTML pages are in %BUILDDIR%/dirhtml.
goto end
)
if "%1" == "singlehtml" (
%SPHINXBUILD% -b singlehtml %ALLSPHINXOPTS% %BUILDDIR%/singlehtml
if errorlevel 1 exit /b 1
echo.
echo.Build finished. The HTML pages are in %BUILDDIR%/singlehtml.
goto end
)
if "%1" == "pickle" (
%SPHINXBUILD% -b pickle %ALLSPHINXOPTS% %BUILDDIR%/pickle
if errorlevel 1 exit /b 1
echo.
echo.Build finished; now you can process the pickle files.
goto end
)
if "%1" == "json" (
%SPHINXBUILD% -b json %ALLSPHINXOPTS% %BUILDDIR%/json
if errorlevel 1 exit /b 1
echo.
echo.Build finished; now you can process the JSON files.
goto end
)
if "%1" == "htmlhelp" (
%SPHINXBUILD% -b htmlhelp %ALLSPHINXOPTS% %BUILDDIR%/htmlhelp
if errorlevel 1 exit /b 1
echo.
echo.Build finished; now you can run HTML Help Workshop with the ^
.hhp project file in %BUILDDIR%/htmlhelp.
goto end
)
if "%1" == "epub" (
%SPHINXBUILD% -b epub %ALLSPHINXOPTS% %BUILDDIR%/epub
if errorlevel 1 exit /b 1
echo.
echo.Build finished. The epub file is in %BUILDDIR%/epub.
goto end
)
if "%1" == "latex" (
%SPHINXBUILD% -b latex %ALLSPHINXOPTS% %BUILDDIR%/latex
if errorlevel 1 exit /b 1
echo.
echo.Build finished; the LaTeX files are in %BUILDDIR%/latex.
goto end
)
if "%1" == "latexpdf" (
%SPHINXBUILD% -b latex %ALLSPHINXOPTS% %BUILDDIR%/latex
cd %BUILDDIR%/latex
make all-pdf
cd %BUILDDIR%/..
echo.
echo.Build finished; the PDF files are in %BUILDDIR%/latex.
goto end
)
if "%1" == "latexpdfja" (
%SPHINXBUILD% -b latex %ALLSPHINXOPTS% %BUILDDIR%/latex
cd %BUILDDIR%/latex
make all-pdf-ja
cd %BUILDDIR%/..
echo.
echo.Build finished; the PDF files are in %BUILDDIR%/latex.
goto end
)
if "%1" == "text" (
%SPHINXBUILD% -b text %ALLSPHINXOPTS% %BUILDDIR%/text
if errorlevel 1 exit /b 1
echo.
echo.Build finished. The text files are in %BUILDDIR%/text.
goto end
)
if "%1" == "man" (
%SPHINXBUILD% -b man %ALLSPHINXOPTS% %BUILDDIR%/man
if errorlevel 1 exit /b 1
echo.
echo.Build finished. The manual pages are in %BUILDDIR%/man.
goto end
)
if "%1" == "texinfo" (
%SPHINXBUILD% -b texinfo %ALLSPHINXOPTS% %BUILDDIR%/texinfo
if errorlevel 1 exit /b 1
echo.
echo.Build finished. The Texinfo files are in %BUILDDIR%/texinfo.
goto end
)
if "%1" == "gettext" (
%SPHINXBUILD% -b gettext %I18NSPHINXOPTS% %BUILDDIR%/locale
if errorlevel 1 exit /b 1
echo.
echo.Build finished. The message catalogs are in %BUILDDIR%/locale.
goto end
)
if "%1" == "changes" (
%SPHINXBUILD% -b changes %ALLSPHINXOPTS% %BUILDDIR%/changes
if errorlevel 1 exit /b 1
echo.
echo.The overview file is in %BUILDDIR%/changes.
goto end
)
if "%1" == "linkcheck" (
%SPHINXBUILD% -b linkcheck %ALLSPHINXOPTS% %BUILDDIR%/linkcheck
if errorlevel 1 exit /b 1
echo.
echo.Link check complete; look for any errors in the above output ^
or in %BUILDDIR%/linkcheck/output.txt.
goto end
)
if "%1" == "doctest" (
%SPHINXBUILD% -b doctest %ALLSPHINXOPTS% %BUILDDIR%/doctest
if errorlevel 1 exit /b 1
echo.
echo.Testing of doctests in the sources finished, look at the ^
results in %BUILDDIR%/doctest/output.txt.
goto end
)
if "%1" == "xml" (
%SPHINXBUILD% -b xml %ALLSPHINXOPTS% %BUILDDIR%/xml
if errorlevel 1 exit /b 1
echo.
echo.Build finished. The XML files are in %BUILDDIR%/xml.
goto end
)
if "%1" == "pseudoxml" (
%SPHINXBUILD% -b pseudoxml %ALLSPHINXOPTS% %BUILDDIR%/pseudoxml
if errorlevel 1 exit /b 1
echo.
echo.Build finished. The pseudo-XML files are in %BUILDDIR%/pseudoxml.
goto end
)
:end

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"""Sphinx ReadTheDocs theme.
From https://github.com/ryan-roemer/sphinx-bootstrap-theme.
"""
import os
VERSION = (0, 1, 6)
__version__ = ".".join(str(v) for v in VERSION)
__version_full__ = __version__
def get_html_theme_path():
"""Return list of HTML theme paths."""
cur_dir = os.path.abspath(os.path.dirname(os.path.dirname(__file__)))
return cur_dir

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misoclib/tools/doc/source/_themes/enjoydigital_sphinx_rtd_theme/breadcrumbs.html Normal file
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<div role="navigation" aria-label="breadcrumbs navigation">
<div class="breadcrumb-box">
<a class="breadcrumb-box-item" href="{{ pathto(master_doc) }}">Home</a>
{% for doc in parents %}
<a class="breadcrumb-box-item" href="{{ doc.link|e }}">&raquo;&nbsp;{{ doc.title }}</a>
{% endfor %}
<div class="breadcrumb-box-item">&raquo;&nbsp;{{ title }}</div>
</div>
</div>

100
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<footer>
{% if next or prev %}
<div class="rst-footer-buttons" role="navigation" aria-label="footer navigation">
{% if next %}
<a href="{{ next.link|e }}" class="btn btn-neutral float-right" title="{{ next.title|striptags|e }}"/>Next <span class="fa fa-arrow-circle-right"></span></a>
{% endif %}
{% if prev %}
<a href="{{ prev.link|e }}" class="btn btn-neutral" title="{{ prev.title|striptags|e }}"><span class="fa fa-arrow-circle-left"></span> Previous</a>
{% endif %}
</div>
{% endif %}
<!--begin hamishw addition -->
<!-- -->
<!--Footer important links
If no such page exists then nav item is not created. CSS defines which of the long or short version is
displayed. -->
{% set footer_links = [
('docs/getting_started/bug_reports', 'Report Bug', 'Report Bug'),
('docs/introducing_litescope/license', 'Licensing', 'Licensing'),
('docs/contributing/contributing', 'Contributing', 'Contributing'),
('docs/introducing_litescope/release_notes', 'Release notes', 'Release notes'),
('docs/introducing_litescope/community', 'Help', 'Contact'),
] -%}
<div class="footer-nav-bar" style="">
<div class="footer-options">
{% for document, shorttext, longtext in footer_links %}
{%- if hasdoc(document) %}
<a class="footer-navlink-short" title="{{ shorttext }}" href="{{ pathto(document) }}">{{ shorttext }}</a><a class="footer-navlink-long" title="{{ longtext }}" href="{{ pathto(document) }}">{{ longtext }}</a>
{%- elif document | truncate(4, True, end='') == 'http' %}
<a class="footer-navlink-short external" href="{{ document }}">{{ shorttext }}</a><a class="footer-navlink-long external" href="{{ document }}">{{ longtext }}</a>
{%- else %}
{{ shorttext }}
{%- endif %}
{% endfor %}
</div>
</div>
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<div role="contentinfo" class="copyright-box">
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<ul class="wy-breadcrumbs">
<li class="wy-breadcrumbs-aside">
{% if display_github %}
<a href="https://github.com/{{ github_user }}/{{ github_repo }}/blob/{{ github_version }}{{ conf_py_path }}{{ pagename }}.rst" class="fa fa-github"> Edit on GitHub</a>
{% elif display_bitbucket %}
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{% elif show_source and has_source and sourcename %}
<a href="{{ pathto('_sources/' + sourcename, true)|e }}" rel="nofollow"> View page source</a>
{% endif %}
</li>
<li class="wy-breadcrumbs-aside">
{%- if hasdoc('docs/site/about') %}
<a href="{{pathto('docs/site/about')}}">About site</a>
{%- endif %}
</li>
</ul>
<p>
{%- if show_copyright %}
{%- if hasdoc('copyright') %}
{% trans path=pathto('copyright'), copyright=copyright|e %}&copy; <a href="{{ path }}">Copyright</a> {{ copyright }}.{% endtrans %}
{%- else %}
<!-- {% trans copyright=copyright|e %}&copy; Copyright {{ copyright }}.{% endtrans %} -->
&copy; Copyright {{ copyright }} <a href="{{ pathto("docs\contributing\AUTHORS") }}">EnjoyDigital and M-Labs Contributors</a>.
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{%- endif %}
{%- endif %}
{%- if last_updated %}
{% trans last_updated=last_updated|e %}Last updated on {{ last_updated }}.{% endtrans %}
{%- endif %}
</p>
</div>
</footer>

208
misoclib/tools/doc/source/_themes/enjoydigital_sphinx_rtd_theme/layout.html Normal file
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{# TEMPLATE VAR SETTINGS #}
{%- set url_root = pathto('', 1) %}
{%- if url_root == '#' %}{% set url_root = '' %}{% endif %}
{%- if not embedded and docstitle %}
{%- set titlesuffix = " &mdash; "|safe + docstitle|e %}
{%- else %}
{%- set titlesuffix = "" %}
{%- endif %}
<!DOCTYPE html>
<!--[if IE 8]><html class="no-js lt-ie9" lang="en" > <![endif]-->
<!--[if gt IE 8]><!--> <html class="no-js" lang="en" > <!--<![endif]-->
<head>
<meta charset="utf-8">
<meta name="viewport" content="width=device-width, initial-scale=1.0">
{% block htmltitle %}
<title>{{ title|striptags|e }}{{ titlesuffix }}</title>
{% endblock %}
{# FAVICON #}
{% if favicon %}
<link rel="shortcut icon" href="{{ pathto('_static/' + favicon, 1) }}"/>
{% endif %}
{# CSS #}
<link href='https://fonts.googleapis.com/css?family=Lato:400,700|Roboto+Slab:400,700|Inconsolata:400,700' rel='stylesheet' type='text/css'>
{# OPENSEARCH #}
{% if not embedded %}
{% if use_opensearch %}
<link rel="search" type="application/opensearchdescription+xml" title="{% trans docstitle=docstitle|e %}Search within {{ docstitle }}{% endtrans %}" href="{{ pathto('_static/opensearch.xml', 1) }}"/>
{% endif %}
{% endif %}
{# RTD hosts this file, so just load on non RTD builds #}
{% if not READTHEDOCS %}
<link rel="stylesheet" href="{{ pathto('_static/' + style, 1) }}" type="text/css" />
{% endif %}
{% for cssfile in css_files %}
<link rel="stylesheet" href="{{ pathto(cssfile, 1) }}" type="text/css" />
{% endfor %}
{%- block linktags %}
{%- if hasdoc('about') %}
<link rel="author" title="{{ _('About these documents') }}"
href="{{ pathto('about') }}"/>
{%- endif %}
{%- if hasdoc('genindex') %}
<link rel="index" title="{{ _('Index') }}"
href="{{ pathto('genindex') }}"/>
{%- endif %}
{%- if hasdoc('search') %}
<link rel="search" title="{{ _('Search') }}" href="{{ pathto('search') }}"/>
{%- endif %}
{%- if hasdoc('copyright') %}
<link rel="copyright" title="{{ _('Copyright') }}" href="{{ pathto('copyright') }}"/>
{%- endif %}
<link rel="top" title="{{ docstitle|e }}" href="{{ pathto('index') }}"/>
{%- if parents %}
<link rel="up" title="{{ parents[-1].title|striptags|e }}" href="{{ parents[-1].link|e }}"/>
{%- endif %}
{%- if next %}
<link rel="next" title="{{ next.title|striptags|e }}" href="{{ next.link|e }}"/>
{%- endif %}
{%- if prev %}
<link rel="prev" title="{{ prev.title|striptags|e }}" href="{{ prev.link|e }}"/>
{%- endif %}
{%- endblock %}
{%- block extrahead %} {% endblock %}
{# Keep modernizr in head - http://modernizr.com/docs/#installing #}
<script src="https://cdnjs.cloudflare.com/ajax/libs/modernizr/2.6.2/modernizr.min.js"></script>
</head>
<body class="wy-body-for-nav" role="document">
<div class="grid-to-center-rtd-theme">
<div class="wy-grid-for-nav">
{# SIDE NAV, TOGGLES ON MOBILE #}
<nav data-toggle="wy-nav-shift" class="wy-nav-side">
<div class="wy-side-nav-search">
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<a href="{{ pathto(master_doc) }}"> <img src="{{ url_root }}/_static/{{ logo }}" alt="Logo" /> </a>
{% include "searchbox.html" %}
</div>
<div class="wy-menu wy-menu-vertical" data-spy="affix" role="navigation" aria-label="main navigation">
{% set toctree = toctree(maxdepth=4, collapse=False, includehidden=True) %}
{% if toctree %}
{{ toctree }}
<a class="toctree-l1" title="Index" href="{{ pathto('genindex') }}">Index</a>
{% else %}
<!-- Local TOC -->
<div class="local-toc">{{ toc }}</div>
{% endif %}
</div>
&nbsp;
</nav>
<section data-toggle="wy-nav-shift" class="wy-nav-content-wrap">
{# MOBILE NAV, TRIGGLES SIDE NAV ON TOGGLE #}
<nav class="wy-nav-top" role="navigation" aria-label="top navigation">
<i data-toggle="wy-nav-top" class="fa fa-bars"></i>
<!-- <a href="{{ pathto(master_doc) }}">{{ project }}</a> -->
<a href="{{ pathto(master_doc) }}"> <img src="{{ url_root }}/_static/{{ logo }}" alt="Logo" /> </a>
</nav>
{# PAGE CONTENT #}
<div class="wy-nav-content">
<div class="rst-content">
<!--begin hamishw addition -->
<!--Nav bar defined as a document followed by short version of nav text and long version
If no such page exists then nav item is not created. CSS defines which of the long or short version is
displayed. -->
{% set navigation_bar = [
('docs/index', 'Docs', 'Documentation'),
('docs/getting_started/downloads', 'SDK', 'Downloads'),
('docs/introducing_litescope/community', 'Help', 'Community'),
('https://github.com/enjoy-digital/litescope', 'Github', 'Github Project')
] -%}
<div class="main-nav-bar" style="">
<!-- the layout of the menu options - centered with left and right alignment of the first and last loop items respectively.
This is VERY UGLY as I'm adding to the CSS in the code to force the alignment. Would be better just to have the elements here and have the CSS in the CSS file. This could be done with a CSS selector, but not worked out how yet. -->
<ul id="menu-options">
{% for document, shorttext, longtext in navigation_bar %}
{%- if hasdoc(document) %}
<li{%- if loop.first %} style="text-align:left;" {%- endif %}{%- if loop.last %} style="text-align:right;" {%- endif %}><a class="navlink-short" title="{{ shorttext }}" href="{{ pathto(document) }}">{{ shorttext }}</a><a class="navlink-long" title="{{ longtext }}" href="{{ pathto(document) }}">{{ longtext }}</a></li>
{%- elif document | truncate(4, True, end='') == 'http' %}
<li{%- if loop.first %} style="text-align:left;" {%- endif %}{%- if loop.last %} style="text-align:right;" {%- endif %}><a class="navlink-short external" href="{{ document }}">{{ shorttext }}</a><a class="navlink-long external" href="{{ document }}">{{ longtext }}</a></li>
{%- endif %}
{% endfor %}
</ul>
<!-- <div style="clear:both;"></div> -->
{% include "breadcrumbs.html" %}
</div>
<!--end hamishw addition -->
<!--HamishW move {% include "breadcrumbs.html" %} -->
<div role="main">
{% block body %}{% endblock %}
</div>
{% include "footer.html" %}
</div>
</div>
</section>
</div>
{% include "versions.html" %}
{% if not embedded %}
<script type="text/javascript">
var DOCUMENTATION_OPTIONS = {
URL_ROOT:'{{ url_root }}',
VERSION:'{{ release|e }}',
COLLAPSE_INDEX:false,
FILE_SUFFIX:'{{ '' if no_search_suffix else file_suffix }}',
HAS_SOURCE: {{ has_source|lower }}
};
</script>
{%- for scriptfile in script_files %}
<script type="text/javascript" src="{{ pathto(scriptfile, 1) }}"></script>
{%- endfor %}
{% endif %}
{# RTD hosts this file, so just load on non RTD builds #}
{% if not READTHEDOCS %}
<script type="text/javascript" src="{{ pathto('_static/js/theme.js', 1) }}"></script>
{% endif %}
{# STICKY NAVIGATION #}
{% if theme_sticky_navigation %}
<script type="text/javascript">
jQuery(function () {
SphinxRtdTheme.StickyNav.enable();
});
</script>
{% endif %}
{%- block footer %} {% endblock %}
</div>
</body>
</html>

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{#
basic/layout.html
~~~~~~~~~~~~~~~~~
Master layout template for Sphinx themes.
:copyright: Copyright 2007-2013 by the Sphinx team, see AUTHORS.
:license: BSD, see LICENSE for details.
#}
{%- block doctype -%}
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
{%- endblock %}
{%- set reldelim1 = reldelim1 is not defined and ' &raquo;' or reldelim1 %}
{%- set reldelim2 = reldelim2 is not defined and ' |' or reldelim2 %}
{%- set render_sidebar = (not embedded) and (not theme_nosidebar|tobool) and
(sidebars != []) %}
{%- set url_root = pathto('', 1) %}
{# XXX necessary? #}
{%- if url_root == '#' %}{% set url_root = '' %}{% endif %}
{%- if not embedded and docstitle %}
{%- set titlesuffix = " &mdash; "|safe + docstitle|e %}
{%- else %}
{%- set titlesuffix = "" %}
{%- endif %}
{%- macro relbar() %}
<div class="related">
<h3>{{ _('Navigation') }}</h3>
<ul>
{%- for rellink in rellinks %}
<li class="right" {% if loop.first %}style="margin-right: 10px"{% endif %}>
<a href="{{ pathto(rellink[0]) }}" title="{{ rellink[1]|striptags|e }}"
{{ accesskey(rellink[2]) }}>{{ rellink[3] }}</a>
{%- if not loop.first %}{{ reldelim2 }}{% endif %}</li>
{%- endfor %}
{%- block rootrellink %}
<li><a href="{{ pathto(master_doc) }}">{{ shorttitle|e }}</a>{{ reldelim1 }}</li>
{%- endblock %}
{%- for parent in parents %}
<li><a href="{{ parent.link|e }}" {% if loop.last %}{{ accesskey("U") }}{% endif %}>{{ parent.title }}</a>{{ reldelim1 }}</li>
{%- endfor %}
{%- block relbaritems %} {% endblock %}
</ul>
</div>
{%- endmacro %}
{%- macro sidebar() %}
{%- if render_sidebar %}
<div class="sphinxsidebar">
<div class="sphinxsidebarwrapper">
{%- block sidebarlogo %}
{%- if logo %}
<p class="logo"><a href="{{ pathto(master_doc) }}">
<img class="logo" src="{{ pathto('_static/' + logo, 1) }}" alt="Logo"/>
</a></p>
{%- endif %}
{%- endblock %}
{%- if sidebars != None %}
{#- new style sidebar: explicitly include/exclude templates #}
{%- for sidebartemplate in sidebars %}
{%- include sidebartemplate %}
{%- endfor %}
{%- else %}
{#- old style sidebars: using blocks -- should be deprecated #}
{%- block sidebartoc %}
{%- include "localtoc.html" %}
{%- endblock %}
{%- block sidebarrel %}
{%- include "relations.html" %}
{%- endblock %}
{%- block sidebarsourcelink %}
{%- include "sourcelink.html" %}
{%- endblock %}
{%- if customsidebar %}
{%- include customsidebar %}
{%- endif %}
{%- block sidebarsearch %}
{%- include "searchbox.html" %}
{%- endblock %}
{%- endif %}
</div>
</div>
{%- endif %}
{%- endmacro %}
{%- macro script() %}
<script type="text/javascript">
var DOCUMENTATION_OPTIONS = {
URL_ROOT: '{{ url_root }}',
VERSION: '{{ release|e }}',
COLLAPSE_INDEX: false,
FILE_SUFFIX: '{{ '' if no_search_suffix else file_suffix }}',
HAS_SOURCE: {{ has_source|lower }}
};
</script>
{%- for scriptfile in script_files %}
<script type="text/javascript" src="{{ pathto(scriptfile, 1) }}"></script>
{%- endfor %}
{%- endmacro %}
{%- macro css() %}
<link rel="stylesheet" href="{{ pathto('_static/' + style, 1) }}" type="text/css" />
<link rel="stylesheet" href="{{ pathto('_static/pygments.css', 1) }}" type="text/css" />
{%- for cssfile in css_files %}
<link rel="stylesheet" href="{{ pathto(cssfile, 1) }}" type="text/css" />
{%- endfor %}
{%- endmacro %}
<html xmlns="http://www.w3.org/1999/xhtml">
<head>
<meta http-equiv="Content-Type" content="text/html; charset={{ encoding }}" />
{{ metatags }}
{%- block htmltitle %}
<title>{{ title|striptags|e }}{{ titlesuffix }}</title>
{%- endblock %}
{{ css() }}
{%- if not embedded %}
{{ script() }}
{%- if use_opensearch %}
<link rel="search" type="application/opensearchdescription+xml"
title="{% trans docstitle=docstitle|e %}Search within {{ docstitle }}{% endtrans %}"
href="{{ pathto('_static/opensearch.xml', 1) }}"/>
{%- endif %}
{%- if favicon %}
<link rel="shortcut icon" href="{{ pathto('_static/' + favicon, 1) }}"/>
{%- endif %}
{%- endif %}
{%- block linktags %}
{%- if hasdoc('about') %}
<link rel="author" title="{{ _('About these documents') }}" href="{{ pathto('about') }}" />
{%- endif %}
{%- if hasdoc('genindex') %}
<link rel="index" title="{{ _('Index') }}" href="{{ pathto('genindex') }}" />
{%- endif %}
{%- if hasdoc('search') %}
<link rel="search" title="{{ _('Search') }}" href="{{ pathto('search') }}" />
{%- endif %}
{%- if hasdoc('copyright') %}
<link rel="copyright" title="{{ _('Copyright') }}" href="{{ pathto('copyright') }}" />
{%- endif %}
<link rel="top" title="{{ docstitle|e }}" href="{{ pathto('index') }}" />
{%- if parents %}
<link rel="up" title="{{ parents[-1].title|striptags|e }}" href="{{ parents[-1].link|e }}" />
{%- endif %}
{%- if next %}
<link rel="next" title="{{ next.title|striptags|e }}" href="{{ next.link|e }}" />
{%- endif %}
{%- if prev %}
<link rel="prev" title="{{ prev.title|striptags|e }}" href="{{ prev.link|e }}" />
{%- endif %}
{%- endblock %}
{%- block extrahead %} {% endblock %}
</head>
<body>
{%- block header %}{% endblock %}
{%- block relbar1 %}{{ relbar() }}{% endblock %}
{%- block content %}
{%- block sidebar1 %} {# possible location for sidebar #} {% endblock %}
<div class="document">
{%- block document %}
<div class="documentwrapper">
{%- if render_sidebar %}
<div class="bodywrapper">
{%- endif %}
<div class="body">
{% block body %} {% endblock %}
</div>
{%- if render_sidebar %}
</div>
{%- endif %}
</div>
{%- endblock %}
{%- block sidebar2 %}{{ sidebar() }}{% endblock %}
<div class="clearer"></div>
</div>
{%- endblock %}
{%- block relbar2 %}{{ relbar() }}{% endblock %}
{%- block footer %}
<div class="footer">
{%- if show_copyright %}
{%- if hasdoc('copyright') %}
{% trans path=pathto('copyright'), copyright=copyright|e %}&copy; <a href="{{ path }}">Copyright</a> {{ copyright }}.{% endtrans %}
{%- else %}
{% trans copyright=copyright|e %}&copy; Copyright {{ copyright }}.{% endtrans %}
{%- endif %}
{%- endif %}
{%- if last_updated %}
{% trans last_updated=last_updated|e %}Last updated on {{ last_updated }}.{% endtrans %}
{%- endif %}
{%- if show_sphinx %}
{% trans sphinx_version=sphinx_version|e %}Created using <a href="http://sphinx-doc.org/">Sphinx</a> {{ sphinx_version }}.{% endtrans %}
{%- endif %}
</div>
<p>asdf asdf asdf asdf 22</p>
{%- endblock %}
</body>
</html>

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{#
basic/search.html
~~~~~~~~~~~~~~~~~
Template for the search page.
:copyright: Copyright 2007-2013 by the Sphinx team, see AUTHORS.
:license: BSD, see LICENSE for details.
#}
{%- extends "layout.html" %}
{% set title = _('Search') %}
{% set script_files = script_files + ['_static/searchtools.js'] %}
{% block footer %}
<script type="text/javascript">
jQuery(function() { Search.loadIndex("{{ pathto('searchindex.js', 1) }}"); });
</script>
{# this is used when loading the search index using $.ajax fails,
such as on Chrome for documents on localhost #}
<script type="text/javascript" id="searchindexloader"></script>
{{ super() }}
{% endblock %}
{% block body %}
<noscript>
<div id="fallback" class="admonition warning">
<p class="last">
{% trans %}Please activate JavaScript to enable the search
functionality.{% endtrans %}
</p>
</div>
</noscript>
{% if search_performed %}
<h2>{{ _('Search Results') }}</h2>
{% if not search_results %}
<p>{{ _('Your search did not match any documents. Please make sure that all words are spelled correctly and that you\'ve selected enough categories.') }}</p>
{% endif %}
{% endif %}
<div id="search-results">
{% if search_results %}
<ul>
{% for href, caption, context in search_results %}
<li>
<a href="{{ pathto(item.href) }}">{{ caption }}</a>
<p class="context">{{ context|e }}</p>
</li>
{% endfor %}
</ul>
{% endif %}
</div>
{% endblock %}

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<div role="search">
<form id ="rtd-search-form" class="wy-form" action="{{ pathto('search') }}" method="get">
<input type="text" name="q" placeholder="Search docs" />
<input type="hidden" name="check_keywords" value="yes" />
<input type="hidden" name="area" value="default" />
</form>
</div>

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[theme]
inherit = basic
stylesheet = css/theme.css
[options]
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{% if READTHEDOCS %}
{# Add rst-badge after rst-versions for small badge style. #}
<div class="rst-versions" data-toggle="rst-versions" role="note" aria-label="versions">
<span class="rst-current-version" data-toggle="rst-current-version">
<span class="fa fa-book"> Read the Docs</span>
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<span class="fa fa-caret-down"></span>
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<dt>Versions</dt>
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{% endfor %}
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# -*- coding: utf-8 -*-
#
# LiteScope documentation build configuration file, created by
# sphinx-quickstart on Tue Jul 01 09:20:29 2014.
#
# This file is execfile()d with the current directory set to its
# containing dir.
#
# Note that not all possible configuration values are present in this
# autogenerated file.
#
# All configuration values have a default; values that are commented out
# serve to show the default.
import sys
import os
# At the top. #HamishW https://pypi.python.org/pypi/sphinx-bootstrap-theme/ ...
#import sphinx_bootstrap_theme
# At the top. #HamishW http://sphinx-better-theme.readthedocs.org/en/latest/installation.html easy_install sphinx_better_theme
#from better import better_theme_path
#html_theme_path = [better_theme_path]
# At the top. #HamishW https://github.com/snide/sphinx_rtd_theme easy_install sphinx_rtd_theme
#import sphinx_rtd_theme
#html_theme_path = [sphinx_rtd_theme.get_html_theme_path()]
html_theme_path = ['_themes',]
# If extensions (or modules to document with autodoc) are in another directory,
# add these directories to sys.path here. If the directory is relative to the
# documentation root, use os.path.abspath to make it absolute, like shown here.
#sys.path.insert(0, os.path.abspath('.'))
# -- General configuration ------------------------------------------------
# If your documentation needs a minimal Sphinx version, state it here.
#needs_sphinx = '1.0'
# Add any Sphinx extension module names here, as strings. They can be
# extensions coming with Sphinx (named 'sphinx.ext.*') or your custom
# ones.
extensions = [
'sphinx.ext.autodoc',
'sphinx.ext.doctest',
'sphinx.ext.intersphinx',
'sphinx.ext.todo',
'sphinx.ext.coverage',
'sphinx.ext.ifconfig',
'sphinx.ext.viewcode',
# 'breathe', #added by HamishW
]
#Build "Todo" notes into the source
#todo_include_todos = 'True'
# Add any paths that contain templates here, relative to this directory.
templates_path = ['_templates']
# The suffix of source filenames.
source_suffix = '.rst'
# The encoding of source files.
#source_encoding = 'utf-8-sig'
# The master toctree document.
master_doc = 'index'
# General information about the project.
project = u'LiteScope'
copyright = u'2015, '
# Note, theme was modified to allow this to display (fix breaks the translation code, which was breaking the above link and rendering it as text).
# Also so I could link to specific copyright page.
# The version info for the project you're documenting, acts as replacement for
# |version| and |release|, also used in various other places throughout the
# built documents.
#
litescope_version = open(os.path.abspath(os.path.join(os.path.dirname(os.path.dirname(os.path.dirname(__file__))), 'litescope-version.txt'))).read().strip()
# The short X.Y version.
version = litescope_version[:litescope_version.rindex('.')]
# The full version, including alpha/beta/rc tags.
release = litescope_version
# The language for content autogenerated by Sphinx. Refer to documentation
# for a list of supported languages.
#language = None
# There are two options for replacing |today|: either, you set today to some
# non-false value, then it is used:
#today = ''
# Else, today_fmt is used as the format for a strftime call.
#today_fmt = '%B %d, %Y'
# List of patterns, relative to source directory, that match files and
# directories to ignore when looking for source files.
exclude_patterns = []
# The reST default role (used for this markup: `text`) to use for all
# documents.
#default_role = None
# If true, '()' will be appended to :func: etc. cross-reference text.
#add_function_parentheses = True
# If true, the current module name will be prepended to all description
# unit titles (such as .. function::).
#add_module_names = True
# If true, sectionauthor and moduleauthor directives will be shown in the
# output. They are ignored by default.
#show_authors = False
# The name of the Pygments (syntax highlighting) style to use.
pygments_style = 'sphinx'
# A list of ignored prefixes for module index sorting.
#modindex_common_prefix = []
# If true, keep warnings as "system message" paragraphs in the built documents.
#keep_warnings = False
# -- Options for HTML output ----------------------------------------------
# The theme to use for HTML and HTML Help pages. See the documentation for
# a list of builtin themes.
#html_theme = 'default'
#html_theme = 'sphinxdoc'
#html_theme = 'agogo' #like this
#html_theme = 'scrolls'
#html_theme = 'bootstrap'
#html_theme_path = sphinx_bootstrap_theme.get_html_theme_path()
#html_theme = 'better'
#html_theme = 'pyramid'
#html_theme = 'nature'
#html_theme = 'haiku'
#html_theme = "sphinx_rtd_theme"
html_theme = "enjoydigital_sphinx_rtd_theme"
# Theme options are theme-specific and customize the look and feel of a theme
# further. For a list of options available for each theme, see the
# documentation.
#html_theme_options = {
# "rightsidebar": "true",
# "relbarbgcolor": "black"
#}
# Add any paths that contain custom themes here, relative to this directory.
#html_theme_path = []
# The name for this set of Sphinx documents. If None, it defaults to
# "<project> v<release> documentation".
#html_title = None
# A shorter title for the navigation bar. Default is the same as html_title.
#html_short_title = None
# The name of an image file (relative to this directory) to place at the top
# of the sidebar.
html_logo = '_static/LiteScope_logo_full.png'
# The name of an image file (within the static path) to use as favicon of the
# docs. This file should be a Windows icon file (.ico) being 16x16 or 32x32
# pixels large.
html_favicon = 'litescope.ico'
# Add any paths that contain custom static files (such as style sheets) here,
# relative to this directory. They are copied after the builtin static files,
# so a file named "default.css" will overwrite the builtin "default.css".
html_static_path = ['_static']
# Add any extra paths that contain custom files (such as robots.txt or
# .htaccess) here, relative to this directory. These files are copied
# directly to the root of the documentation.
#html_extra_path = []
# If not '', a 'Last updated on:' timestamp is inserted at every page bottom,
# using the given strftime format.
#html_last_updated_fmt = '%b %d, %Y'
# If true, SmartyPants will be used to convert quotes and dashes to
# typographically correct entities.
#html_use_smartypants = True
# Custom sidebar templates, maps document names to template names.
#html_sidebars = {}
# Additional templates that should be rendered to pages, maps page names to
# template names.
#html_additional_pages = {}
# If false, no module index is generated.
#html_domain_indices = True
# If false, no index is generated.
#html_use_index = True
# If true, the index is split into individual pages for each letter.
#html_split_index = False
# If true, links to the reST sources are added to the pages.
#html_show_sourcelink = True
# If true, "Created using Sphinx" is shown in the HTML footer. Default is True.
#html_show_sphinx = True
# If true, "(C) Copyright ..." is shown in the HTML footer. Default is True.
#html_show_copyright = True
# If true, an OpenSearch description file will be output, and all pages will
# contain a <link> tag referring to it. The value of this option must be the
# base URL from which the finished HTML is served.
#html_use_opensearch = ''
# This is the file name suffix for HTML files (e.g. ".xhtml").
#html_file_suffix = None
# Output file base name for HTML help builder.
htmlhelp_basename = 'LiteScopedoc'
# -- Options for LaTeX output ---------------------------------------------
latex_elements = {
# The paper size ('letterpaper' or 'a4paper').
#'papersize': 'letterpaper',
# The font size ('10pt', '11pt' or '12pt').
#'pointsize': '10pt',
# Additional stuff for the LaTeX preamble.
#'preamble': '',
}
# Grouping the document tree into LaTeX files. List of tuples
# (source start file, target name, title,
# author, documentclass [howto, manual, or own class]).
latex_documents = [
('index', 'LiteScope.tex', u'LiteScope Documentation',
u'Kermarrec Florent', 'manual'),
]
# The name of an image file (relative to this directory) to place at the top of
# the title page.
#latex_logo = None
# For "manual" documents, if this is true, then toplevel headings are parts,
# not chapters.
#latex_use_parts = False
# If true, show page references after internal links.
#latex_show_pagerefs = False
# If true, show URL addresses after external links.
#latex_show_urls = False
# Documents to append as an appendix to all manuals.
#latex_appendices = []
# If false, no module index is generated.
#latex_domain_indices = True
# -- Options for manual page output ---------------------------------------
# One entry per manual page. List of tuples
# (source start file, name, description, authors, manual section).
man_pages = [
('index', 'litescope', u'LiteScope Documentation',
[u'Florent Kermarrec'], 1)
]
# If true, show URL addresses after external links.
#man_show_urls = False
# -- Options for Texinfo output -------------------------------------------
# Grouping the document tree into Texinfo files. List of tuples
# (source start file, target name, title, author,
# dir menu entry, description, category)
texinfo_documents = [
('index', 'LiteScope', u'LiteScope Documentation',
u'Florent Kermarrec', 'LiteScope', 'One line description of project.',
'Miscellaneous'),
]
# Documents to append as an appendix to all manuals.
#texinfo_appendices = []
# If false, no module index is generated.
#texinfo_domain_indices = True
# How to display URL addresses: 'footnote', 'no', or 'inline'.
#texinfo_show_urls = 'footnote'
# If true, do not generate a @detailmenu in the "Top" node's menu.
#texinfo_no_detailmenu = False
# -- Options for Epub output ----------------------------------------------
# Bibliographic Dublin Core info.
epub_title = u'LiteScope'
epub_author = u'Florent Kermarrec'
epub_publisher = u'Florent Kermarrec'
epub_copyright = u'2015, LiteScope Contributors'
# The basename for the epub file. It defaults to the project name.
#epub_basename = u'LiteScope'
# The HTML theme for the epub output. Since the default themes are not optimized
# for small screen space, using the same theme for HTML and epub output is
# usually not wise. This defaults to 'epub', a theme designed to save visual
# space.
#epub_theme = 'epub'
# The language of the text. It defaults to the language option
# or en if the language is not set.
#epub_language = ''
# The scheme of the identifier. Typical schemes are ISBN or URL.
#epub_scheme = ''
# The unique identifier of the text. This can be a ISBN number
# or the project homepage.
#epub_identifier = ''
# A unique identification for the text.
#epub_uid = ''
# A tuple containing the cover image and cover page html template filenames.
#epub_cover = ()
# A sequence of (type, uri, title) tuples for the guide element of content.opf.
#epub_guide = ()
# HTML files that should be inserted before the pages created by sphinx.
# The format is a list of tuples containing the path and title.
#epub_pre_files = []
# HTML files shat should be inserted after the pages created by sphinx.
# The format is a list of tuples containing the path and title.
#epub_post_files = []
# A list of files that should not be packed into the epub file.
epub_exclude_files = ['search.html']
# The depth of the table of contents in toc.ncx.
#epub_tocdepth = 3
# Allow duplicate toc entries.
#epub_tocdup = True
# Choose between 'default' and 'includehidden'.
#epub_tocscope = 'default'
# Fix unsupported image types using the PIL.
#epub_fix_images = False
# Scale large images.
#epub_max_image_width = 0
# How to display URL addresses: 'footnote', 'no', or 'inline'.
#epub_show_urls = 'inline'
# If false, no index is generated.
#epub_use_index = True
# Example configuration for intersphinx: refer to the Python standard library.
intersphinx_mapping = {'http://docs.python.org/': None}
# HamishW - set highlighting language.
highlight_language = 'cpp'
# HamishW - set domain (cpp)
primary_domain = 'cpp'
# HamishW - tell Breathe about projects. Breathe is tool to convert Doxygen to Python objects, for import into Sphinx.
#breathe_projects = { "myproject": "/home/me/docproj/doxyxml/", "nutshell":"./headers/xml/", }
# HamishW - Specify a default project:
#breathe_default_project = "nutshell"

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.. _core-index:
========================
Core
========================
.. note::
Please contribute to this document, or support us financially to write it.

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.. _frontend-index:
========================
Frontend
========================
.. note::
Please contribute to this document, or support us financially to write it.

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.. _FAQ:
===
FAQ
===
.. note::
Please contribute to this document.

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.. _bug-reports:
=============
Bug Reporting
=============
- send us feedback and suggestions for improvements
- send us bug reports when something goes wrong
- send us the modifications and improvements you have done to LiteScope.
The use of "git format-patch" is recommended. If your submission is large and
complex and/or you are not sure how to proceed, feel free to discuss with us
about it.

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.. _sdk-download-and-install:
====================
Download and install
====================
1. Install Python3 and your vendor's software
2. Obtain Migen and install it:
- git clone https://github.com/m-labs/migen
- cd migen
- python3 setup.py install
- cd ..
.. note::
In case you have issues with Migen, please retry with our forks at:
https://github.com/enjoy-digital/migen
until new features are merged.
3. Obtain LiteScope
- git clone https://github.com/enjoy-digital/litescope
4. Build and load example design:
- python3 make.py all
5. Test design:
- go to ./test directoryand run:
- python3 test_io.py
- python3 test_la.py

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.. _getting-started-index:
===============
Getting Started
===============
Now you know why LiteScope is :ref:`core for you <about>`, it's time to *get started*.
This section provides a walk-through of :ref:`downloading and installing the tools`.
.. toctree::
:maxdepth: 1
downloads
FAQ
bug_reports

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.. _documentation-home:
========================
LiteScope Documentation
========================
This comprehensive documentation set contains everything you need to know to use LiteScope and integrate it in your design.
**Getting started:**
- :ref:`intro-index` explains what LiteScope does, why it is needed, its limitations and its licensing. It will help you understand whether LiteScope is the right core for you.
- :ref:`getting-started-index` walks you through downloading, installing and using the LiteScope core.
**LiteScope Internals:**
- :ref:`core-index` describes core building blocks.
- :ref:`frontend-index` describes core building blocks.
The full hierarchy of articles, opened to the second level, is shown below.
.. toctree::
:maxdepth: 2
intro/index
getting_started/index
core/index
frontend/index

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.. _about:
================
About LiteScope
================
LiteScope is a small footprint and configurable embedded logic analyzer that you
can use in your FPGA and aims to provide a free, portable and flexible
alternatve to vendor's solutions!
LiteScope is part of LiteX libraries whose aims are to lower entry level of complex
FPGA cores by providing simple, elegant and efficient implementations of
components used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...
The core uses simple and specific streaming buses and will provides in the future
adapters to use standardized AXI or Avalon-ST streaming buses.
Since Python is used to describe the HDL, the core is highly and easily
configurable.
LiteScope uses technologies developed in partnership with M-Labs Ltd:
- Migen enables generating HDL with Python in an efficient way.
- MiSoC provides the basic blocks to build a powerful and small footprint SoC.
LiteScope can be used as a Migen/MiSoC library (by simply installing it
with the provided setup.py) or can be integrated with your standard design flow
by generating the verilog rtl that you will use as a standard core.
LiteScope produces "vcd" files that can be read in your regular waveforms viewer.
Since LiteScope also provides a UART <--> Wishbone brige so you only need 2
external Rx/Tx pins to be ready to debug or control all your Wishbone peripherals!
.. _about-toolchain:
Features
========
- IO peek and poke with LiteScopeIO
- Logic analyser with LiteScopeLA:
- Various triggering modules: Term, Range, Edge (add yours! :)
- Run Length Encoder to "compress" data and increase recording depth
- Subsampling
- Storage qualifier
- Data storage in block rams
Possibles improvements
======================
- add standardized interfaces (AXI, Avalon-ST)
- add protocols analyzers
- add signals injection/generation
- add storage in DRAM
- add storage in HDD with LiteSATA core (to be released soon!)
- add Ethernet Wishbone bridge
- add PCIe Wishbone bridge with LitePCIe (to be released soon!)
- ... See below Support and Consulting :)
Support and Consulting
======================
We love open-source hardware and like sharing our designs with others.
LiteScope is developed and maintained by EnjoyDigital.
If you would like to know more about LiteScope or if you are already a happy user
and would like to extend it for your needs, EnjoyDigital can provide standard
commercial support as well as consulting services.
So feel free to contact us, we'd love to work with you! (and eventually shorten
the list of the possible improvements :)
Contact
=======
E-mail: florent [AT] enjoy-digital.fr

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.. _community:
=========
Community
=========

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.. _intro-index:
======================
Introducing LiteScope
======================
This section explains what LiteScope does, why it is needed, its limitations and its licensing. After reading, you will understand whether LiteScope is the right core for you, and where to go if you have :ref:`further questions <community>`.
.. toctree::
:maxdepth: 1
about
license
release_notes
talks_and_publications

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.. _license:
===================
Open Source License
===================
LiteScope is released under the very permissive two-clause BSD license. Under the
terms of this license, you are authorized to use LiteScope for closed-source
proprietary designs.
Even though we do not require you to do so, those things are awesome, so please
do them if possible:
- tell us that you are using LiteScope
- cite LiteScope in publications related to research it has helped
- send us feedback and suggestions for improvements
- send us bug reports when something goes wrong
- send us the modifications and improvements you have done to LiteScope.
::
Unless otherwise noted, LiteScope is copyright (C) 2015 Florent Kermarrec.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Other authors retain ownership of their contributions. If a submission can
reasonably be considered independently copyrightable, it's yours and we
encourage you to claim it with appropriate copyright notices. This submission
then falls under the "otherwise noted" category. All submissions are strongly
encouraged to use the two-clause BSD license reproduced above.

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.. _release-notes:
=============
Release Notes
=============
.. _ChangeLog:
ChangeLog
=========
0.9.0:
- First 0.9.0 release supporting storage in ram blocks.

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.. _talks-and-publications:
======================
Talks and Publications
======================
- Migen / MiSoC documentation:
- `User guide <http://m-labs.hk/migen.pdf>`_ (`m-labs <https://github.com/m-labs>`_)
- `Tutorial: An introduction to Migen <http://m-labs.hk/migen-tutorial.pdf>`_ (`m-labs <https://github.com/m-labs>`_)
- Migen / MiSoC presentations:
- `Lecture slides <http://m-labs.hk/migen-slides.pdf>`_ (`sbourdeauducq <https://github.com/sbourdeauducq>`_)
- `EHSM 2012 presentation <https://www.youtube.com/watch?v=yxKMsAi_WEA>`_ (`sbourdeauducq <https://github.com/sbourdeauducq>`_)
- `ORCONF2014 <https://www.youtube.com/watch?v=AfEPbw4nREo>`_ (`fallen <https://github.com/fallen>`_)

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<img alt="./_static/LiteScope_logo_full.png" src="_static/LiteScope_logo_full.png">
<h3>A small footprint and configurable embedded FPGA logic analyzer core</b>.</h3>
<div class="container" style="width:100%;margin-bottom:10px;">
<div class="one-third-container" style="width:32%; display:inline-block;">
<div class="signpost" style="display:inline-block; vertical-align:text-top; margin-left:5px;margin-right:5px;">
<div class="signpost-heading" style="font-size:2em; font-style:bold; margin-bottom:10px;">Small footprint</div>
<div class="signpost-body" style=""><p>Thanks to simple and efficient Migen's building blocks and the KISS principe used to develop this core, LiteScope footprint is really small!</p></div>
</div>
</div>
<div class="one-third-container" style="width:32%; display:inline-block; font-style:bold;">
<div class="signpost" style="display:inline-block; vertical-align:text-top; margin-left:5px;margin-right:5px;">
<div class="signpost-heading" style="font-size:2em; font-style:bold; margin-bottom:10px;">Configurable</div>
<div class="signpost-body" style=""><p>LiteScope generates HDL using Migen as a Python meta-language. The core is then easily configurable to fit user's needs! (Data width, storage depth, storage qualifier and so on...)</p></div>
</div>
</div>
<div class="one-third-container" style="width:32%; display:inline-block; font-style:bold;">
<div class="signpost" style="display:inline-block; vertical-align:text-top; margin-left:5px; margin-right:5px;">
<div class="signpost-heading" style="font-size:2em; font-style:bold; margin-bottom:10px;">Portable</div>
<div class="signpost-body" style=""><p>Liscope can target all FPGAs regardless of the vendor, so you keep
your debug methology accross all the FPGA designs you are developing!</p></div>
</div>
</div>
</div>

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.. title:: Main
.. _home-page:
.. raw:: html
:file: home_page_layout.html
-----
News
====
- First 0.9.0 release supporting storage in ram blocks.
.. toctree::
:hidden:
docs/intro/index
docs/getting_started/index
docs/core/index
docs/frontend/index
docs/site/about

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0.9.0

0
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from litescope.common import *
from migen.bus import wishbone
from migen.genlib.misc import chooser
from migen.genlib.cdc import MultiReg
from migen.bank.description import *
from migen.bank.eventmanager import *
from migen.genlib.record import Record
from migen.flow.actor import Sink, Source
class UARTRX(Module):
def __init__(self, pads, tuning_word):
self.source = Source([("d", 8)])
###
uart_clk_rxen = Signal()
phase_accumulator_rx = Signal(32)
rx = Signal()
self.specials += MultiReg(pads.rx, rx)
rx_r = Signal()
rx_reg = Signal(8)
rx_bitcount = Signal(4)
rx_busy = Signal()
rx_done = self.source.stb
rx_data = self.source.d
self.sync += [
rx_done.eq(0),
rx_r.eq(rx),
If(~rx_busy,
If(~rx & rx_r, # look for start bit
rx_busy.eq(1),
rx_bitcount.eq(0),
)
).Else(
If(uart_clk_rxen,
rx_bitcount.eq(rx_bitcount + 1),
If(rx_bitcount == 0,
If(rx, # verify start bit
rx_busy.eq(0)
)
).Elif(rx_bitcount == 9,
rx_busy.eq(0),
If(rx, # verify stop bit
rx_data.eq(rx_reg),
rx_done.eq(1)
)
).Else(
rx_reg.eq(Cat(rx_reg[1:], rx))
)
)
)
]
self.sync += \
If(rx_busy,
Cat(phase_accumulator_rx, uart_clk_rxen).eq(phase_accumulator_rx + tuning_word)
).Else(
Cat(phase_accumulator_rx, uart_clk_rxen).eq(2**31)
)
class UARTTX(Module):
def __init__(self, pads, tuning_word):
self.sink = Sink([("d", 8)])
###
uart_clk_txen = Signal()
phase_accumulator_tx = Signal(32)
pads.tx.reset = 1
tx_reg = Signal(8)
tx_bitcount = Signal(4)
tx_busy = Signal()
self.sync += [
self.sink.ack.eq(0),
If(self.sink.stb & ~tx_busy & ~self.sink.ack,
tx_reg.eq(self.sink.d),
tx_bitcount.eq(0),
tx_busy.eq(1),
pads.tx.eq(0)
).Elif(uart_clk_txen & tx_busy,
tx_bitcount.eq(tx_bitcount + 1),
If(tx_bitcount == 8,
pads.tx.eq(1)
).Elif(tx_bitcount == 9,
pads.tx.eq(1),
tx_busy.eq(0),
self.sink.ack.eq(1),
).Else(
pads.tx.eq(tx_reg[0]),
tx_reg.eq(Cat(tx_reg[1:], 0))
)
)
]
self.sync += [
If(tx_busy,
Cat(phase_accumulator_tx, uart_clk_txen).eq(phase_accumulator_tx + tuning_word)
).Else(
Cat(phase_accumulator_tx, uart_clk_txen).eq(0)
)
]
class UART(Module, AutoCSR):
def __init__(self, pads, clk_freq, baud=115200):
self._tuning_word = CSRStorage(32, reset=int((baud/clk_freq)*2**32))
tuning_word = self._tuning_word.storage
###
self.rx = UARTRX(pads, tuning_word)
self.tx = UARTTX(pads, tuning_word)
self.submodules += self.rx, self.tx
class UARTPads:
def __init__(self):
self.rx = Signal()
self.tx = Signal()
class UARTMux(Module):
def __init__(self, pads):
self.sel = Signal(max=2)
self.shared_pads = UARTPads()
self.bridge_pads = UARTPads()
###
# Route rx pad:
# when sel==0, route it to shared rx and bridge rx
# when sel==1, route it only to bridge rx
self.comb += \
If(self.sel==0,
self.shared_pads.rx.eq(pads.rx),
self.bridge_pads.rx.eq(pads.rx)
).Else(
self.bridge_pads.rx.eq(pads.rx)
)
# Route tx:
# when sel==0, route shared tx to pads tx
# when sel==1, route bridge tx to pads tx
self.comb += \
If(self.sel==0,
pads.tx.eq(self.shared_pads.tx)
).Else(
pads.tx.eq(self.bridge_pads.tx)
)
class LiteScopeUART2WB(Module, AutoCSR):
cmds = {
"write" : 0x01,
"read" : 0x02
}
def __init__(self, pads, clk_freq, baud=115200, share_uart=False):
self.wishbone = wishbone.Interface()
if share_uart:
self._sel = CSRStorage()
###
if share_uart:
uart_mux = UARTMux(pads)
uart = UART(uart_mux.bridge_pads, clk_freq, baud)
self.submodules += uart_mux, uart
self.shared_pads = uart_mux.shared_pads
self.comb += uart_mux.sel.eq(self._sel.storage)
else:
uart = UART(pads, clk_freq, baud)
self.submodules += uart
byte_counter = Counter(bits_sign=3)
word_counter = Counter(bits_sign=8)
self.submodules += byte_counter, word_counter
cmd = Signal(8)
cmd_ce = Signal()
length = Signal(8)
length_ce = Signal()
address = Signal(32)
address_ce = Signal()
data = Signal(32)
rx_data_ce = Signal()
tx_data_ce = Signal()
self.sync += [
If(cmd_ce, cmd.eq(uart.rx.source.d)),
If(length_ce, length.eq(uart.rx.source.d)),
If(address_ce, address.eq(Cat(uart.rx.source.d, address[0:24]))),
If(rx_data_ce,
data.eq(Cat(uart.rx.source.d, data[0:24]))
).Elif(tx_data_ce,
data.eq(self.wishbone.dat_r)
)
]
###
fsm = InsertReset(FSM(reset_state="IDLE"))
timeout = Timeout(clk_freq//10)
self.submodules += fsm, timeout
self.comb += [
timeout.ce.eq(1),
fsm.reset.eq(timeout.reached)
]
fsm.act("IDLE",
timeout.reset.eq(1),
If(uart.rx.source.stb,
cmd_ce.eq(1),
If( (uart.rx.source.d == self.cmds["write"]) |
(uart.rx.source.d == self.cmds["read"]),
NextState("RECEIVE_LENGTH")
),
byte_counter.reset.eq(1),
word_counter.reset.eq(1)
)
)
fsm.act("RECEIVE_LENGTH",
If(uart.rx.source.stb,
length_ce.eq(1),
NextState("RECEIVE_ADDRESS")
)
)
fsm.act("RECEIVE_ADDRESS",
If(uart.rx.source.stb,
address_ce.eq(1),
byte_counter.ce.eq(1),
If(byte_counter.value == 3,
If(cmd == self.cmds["write"],
NextState("RECEIVE_DATA")
).Elif(cmd == self.cmds["read"],
NextState("READ_DATA")
),
byte_counter.reset.eq(1),
)
)
)
fsm.act("RECEIVE_DATA",
If(uart.rx.source.stb,
rx_data_ce.eq(1),
byte_counter.ce.eq(1),
If(byte_counter.value == 3,
NextState("WRITE_DATA"),
byte_counter.reset.eq(1)
)
)
)
self.comb += [
self.wishbone.adr.eq(address + word_counter.value),
self.wishbone.dat_w.eq(data),
self.wishbone.sel.eq(2**flen(self.wishbone.sel)-1)
]
fsm.act("WRITE_DATA",
self.wishbone.stb.eq(1),
self.wishbone.we.eq(1),
self.wishbone.cyc.eq(1),
If(self.wishbone.ack,
word_counter.ce.eq(1),
If(word_counter.value == (length-1),
NextState("IDLE")
).Else(
NextState("RECEIVE_DATA")
)
)
)
fsm.act("READ_DATA",
self.wishbone.stb.eq(1),
self.wishbone.we.eq(0),
self.wishbone.cyc.eq(1),
If(self.wishbone.ack,
tx_data_ce.eq(1),
NextState("SEND_DATA")
)
)
self.comb += \
chooser(data, byte_counter.value, uart.tx.sink.d, n=4, reverse=True)
fsm.act("SEND_DATA",
uart.tx.sink.stb.eq(1),
If(uart.tx.sink.ack,
byte_counter.ce.eq(1),
If(byte_counter.value == 3,
word_counter.ce.eq(1),
If(word_counter.value == (length-1),
NextState("IDLE")
).Else(
NextState("READ_DATA"),
byte_counter.reset.eq(1)
)
)
)
)

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from migen.fhdl.std import *
from migen.bank.description import *
from migen.genlib.fsm import FSM, NextState
from migen.flow.actor import *
from migen.actorlib.fifo import AsyncFIFO, SyncFIFO
from migen.flow.plumbing import Buffer
from migen.fhdl.specials import Memory
def data_layout(dw):
return [("data", dw, DIR_M_TO_S)]
def hit_layout():
return [("hit", 1, DIR_M_TO_S)]
@DecorateModule(InsertReset)
@DecorateModule(InsertCE)
class Counter(Module):
def __init__(self, signal=None, **kwargs):
if signal is None:
self.value = Signal(**kwargs)
else:
self.value = signal
self.width = flen(self.value)
self.sync += self.value.eq(self.value+1)
@DecorateModule(InsertReset)
@DecorateModule(InsertCE)
class Timeout(Module):
def __init__(self, length):
self.reached = Signal()
###
value = Signal(max=length)
self.sync += value.eq(value+1)
self.comb += [
self.reached.eq(value == length)
]

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misoclib/tools/litescope/core/__init__.py Normal file
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misoclib/tools/litescope/core/port.py Normal file
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from litescope.common import *
class LiteScopeTermUnit(Module):
def __init__(self, dw):
self.dw = dw
self.sink = sink = Sink(data_layout(dw))
self.source = source = Source(hit_layout())
self.trig = Signal(dw)
self.mask = Signal(dw)
###
self.comb += [
source.stb.eq(sink.stb),
source.hit.eq((sink.data & self.mask) == self.trig),
sink.ack.eq(source.ack)
]
class LiteScopeTerm(LiteScopeTermUnit, AutoCSR):
def __init__(self, dw):
LiteScopeTermUnit.__init__(self, dw)
self._trig = CSRStorage(dw)
self._mask = CSRStorage(dw)
###
self.comb += [
self.trig.eq(self._trig.storage),
self.mask.eq(self._mask.storage)
]
class LiteScopeRangeDetectorUnit(Module):
def __init__(self, dw):
self.dw = dw
self.sink = sink = Sink(data_layout(dw))
self.source = source = Source(hit_layout())
self.low = Signal(dw)
self.high = Signal(dw)
###
self.comb += [
source.stb.eq(sink.stb),
source.hit.eq((sink.data >= self.low) & (sink.data <= self.high)),
sink.ack.eq(source.ack)
]
class LiteScopeRangeDetector(LiteScopeRangeDetectorUnit, AutoCSR):
def __init__(self, dw):
LiteScopeRangeDetectorUnit.__init__(self, dw)
self._low = CSRStorage(dw)
self._high = CSRStorage(dw)
###
self.comb += [
self.low.eq(self._low.storage),
self.high.eq(self._high.storage)
]
class LiteScopeEdgeDetectorUnit(Module):
def __init__(self, dw):
self.dw = dw
self.sink = sink = Sink(data_layout(dw))
self.source = source = Source(hit_layout())
self.rising_mask = Signal(dw)
self.falling_mask = Signal(dw)
self.both_mask = Signal(dw)
###
self.buffer = Buffer(self.sink.description)
self.comb += Record.connect(self.sink, self.buffer.sink)
rising = Signal(dw)
rising.eq(self.rising_mask & sink.data & ~self.buffer.source.data)
falling = Signal(dw)
falling.eq(self.falling_mask & sink.data & ~self.buffer.source.data)
both = Signal(dw)
both.eq(self.both_mask & sink.data & ~self.buffer.source.data)
self.comb += [
source.stb.eq(sink.stb & self.buffer.source.stb),
self.buffer.source.ack.eq(source.ack),
source.hit.eq(rising | falling | both)
]
class LiteScopeEdgeDetector(LiteScopeEdgeDetectorUnit, AutoCSR):
def __init__(self, dw):
LiteScopeEdgeDetectorUnit.__init__(self, dw)
self._rising = CSRStorage(dw)
self._falling = CSRStorage(dw)
self._both = CSRStorage(dw)
###
self.comb += [
self.rising.eq(self._rising.storage),
self.falling.eq(self._falling.storage),
self.both.eq(self._both.storage)
]

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from litescope.common import *
from migen.flow.plumbing import Buffer
class LiteScopeSubSamplerUnit(Module):
def __init__(self, dw):
self.sink = sink = Sink(data_layout(dw))
self.source = source = Source(data_layout(dw))
self.value = Signal(32)
###
self.submodules.counter = Counter(bits_sign=32)
done = Signal()
self.comb += [
done.eq(self.counter.value >= self.value),
Record.connect(sink, source),
source.stb.eq(sink.stb & done),
self.counter.ce.eq(source.ack),
self.counter.reset.eq(source.stb & source.ack & done)
]
class LiteScopeSubSampler(LiteScopeSubSamplerUnit, AutoCSR):
def __init__(self, dw):
LiteScopeSubSamplerUnit.__init__(self, dw)
self._value = CSRStorage(32)
###
self.comb += self.value.eq(self._value.storage)
class LiteScopeRunLengthEncoderUnit(Module):
def __init__(self, dw, length):
self.dw = dw
self.length = length
self.sink = sink = Sink(data_layout(dw))
self.source = source = Source(data_layout(dw))
self.enable = Signal()
###
self.submodules.buf = buf = Buffer(sink.description)
self.comb += Record.connect(sink, buf.d)
self.submodules.counter = counter = Counter(max=length)
counter_done = Signal()
self.comb += counter_done.eq(counter.value == length-1)
change = Signal()
self.comb += change.eq(
sink.stb &
(sink.data != buf.q.data)
)
self.submodules.fsm = fsm = FSM(reset_state="BYPASS")
fsm.act("BYPASS",
Record.connect(buf.q, source),
counter.reset.eq(1),
If(sink.stb & ~change,
If(self.enable,
NextState("COUNT")
)
)
)
fsm.act("COUNT",
buf.q.ack.eq(1),
counter.ce.eq(sink.stb),
If(~self.enable,
NextState("BYPASS")
).Elif(change | counter_done,
source.stb.eq(1),
source.data[:flen(counter.value)].eq(counter.value),
source.data[-1].eq(1), # Set RLE bit
buf.q.ack.eq(source.ack),
If(source.ack,
NextState("BYPASS")
)
)
)
class LiteScopeRunLengthEncoder(LiteScopeRunLengthEncoderUnit, AutoCSR):
def __init__(self, dw, length=1024):
LiteScopeRunLengthEncoderUnit.__init__(self, dw, length)
self._enable = CSRStorage()
self.external_enable = Signal(reset=1)
###
self.comb += self.enable.eq(self._enable.storage & self.external_enable)
class LiteScopeRecorderUnit(Module):
def __init__(self, dw, depth):
self.dw = dw
self.depth = depth
self.trigger_sink = trigger_sink = Sink(hit_layout())
self.data_sink = data_sink = Sink(data_layout(dw))
self.trigger = Signal()
self.qualifier = Signal()
self.length = Signal(bits_for(depth))
self.offset = Signal(bits_for(depth))
self.done = Signal()
self.post_hit = Signal()
self.source = Source(data_layout(dw))
###
fifo = InsertReset(SyncFIFO(data_layout(dw), depth, buffered=True))
self.submodules += fifo
fsm = FSM(reset_state="IDLE")
self.submodules += fsm
self.comb += [
self.source.stb.eq(fifo.source.stb),
self.source.data.eq(fifo.source.data)
]
fsm.act("IDLE",
self.done.eq(1),
If(self.trigger,
NextState("PRE_HIT_RECORDING"),
fifo.reset.eq(1),
),
fifo.source.ack.eq(self.source.ack)
)
fsm.act("PRE_HIT_RECORDING",
fifo.sink.stb.eq(data_sink.stb),
fifo.sink.data.eq(data_sink.data),
data_sink.ack.eq(fifo.sink.ack),
fifo.source.ack.eq(fifo.fifo.level >= self.offset),
If(trigger_sink.stb & trigger_sink.hit, NextState("POST_HIT_RECORDING"))
)
fsm.act("POST_HIT_RECORDING",
self.post_hit.eq(1),
If(self.qualifier,
fifo.sink.stb.eq(trigger_sink.stb & trigger_sink.hit & data_sink.stb)
).Else(
fifo.sink.stb.eq(data_sink.stb)
),
fifo.sink.data.eq(data_sink.data),
data_sink.ack.eq(fifo.sink.ack),
If(~fifo.sink.ack | (fifo.fifo.level >= self.length), NextState("IDLE"))
)
class LiteScopeRecorder(LiteScopeRecorderUnit, AutoCSR):
def __init__(self, dw, depth):
LiteScopeRecorderUnit.__init__(self, dw, depth)
self._trigger = CSR()
self._qualifier = CSRStorage()
self._length = CSRStorage(bits_for(depth))
self._offset = CSRStorage(bits_for(depth))
self._done = CSRStatus()
self._source_stb = CSRStatus()
self._source_ack = CSR()
self._source_data = CSRStatus(dw)
###
self.comb += [
self.trigger.eq(self._trigger.re),
self.qualifier.eq(self._qualifier.storage),
self.length.eq(self._length.storage),
self.offset.eq(self._offset.storage),
self._done.status.eq(self.done),
self._source_stb.status.eq(self.source.stb),
self._source_data.status.eq(self.source.data),
self.source.ack.eq(self._source_ack.re)
]

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from litescope.common import *
class LiteScopeSumUnit(Module, AutoCSR):
def __init__(self, ports):
self.sinks = sinks = [Sink(hit_layout()) for i in range(ports)]
self.source = source = Source(hit_layout())
self.prog_we = Signal()
self.prog_adr = Signal(ports)
self.prog_dat = Signal()
mem = Memory(1, 2**ports)
lut = mem.get_port()
prog = mem.get_port(write_capable=True)
self.specials += mem, lut, prog
###
# program port
self.comb += [
prog.we.eq(self.prog_we),
prog.adr.eq(self.prog_adr),
prog.dat_w.eq(self.prog_dat)
]
# LUT port
for i, sink in enumerate(sinks):
self.comb += lut.adr[i].eq(sink.hit)
# drive source
self.comb += [
source.stb.eq(optree("&", [sink.stb for sink in sinks])),
source.hit.eq(lut.dat_r)
]
for i, sink in enumerate(sinks):
self.comb += sink.ack.eq(sink.stb & source.ack)
class LiteScopeSum(LiteScopeSumUnit, AutoCSR):
def __init__(self, ports):
LiteScopeSumUnit.__init__(self, ports)
self._prog_we = CSR()
self._prog_adr = CSRStorage(ports)
self._prog_dat = CSRStorage()
###
self.comb += [
self.prog_we.eq(self._prog_we.re & self._prog_we.r),
self.prog_adr.eq(self._prog_adr.storage),
self.prog_dat.eq(self._prog_dat.storage)
]
class LiteScopeTrigger(Module, AutoCSR):
def __init__(self, dw):
self.dw = dw
self.ports = []
self.sink = Sink(data_layout(dw))
self.source = Source(hit_layout())
def add_port(self, port):
setattr(self.submodules, "port"+str(len(self.ports)), port)
self.ports.append(port)
def do_finalize(self):
self.submodules.sum = LiteScopeSum(len(self.ports))
###
for i, port in enumerate(self.ports):
# Note: port's ack is not used and supposed to be always 1
self.comb += [
port.sink.stb.eq(self.sink.stb),
port.sink.data.eq(self.sink.data),
self.sink.ack.eq(1),
Record.connect(port.source, self.sum.sinks[i])
]
self.comb += Record.connect(self.sum.source, self.source)

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misoclib/tools/litescope/frontend/__init__.py Normal file
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misoclib/tools/litescope/frontend/io.py Normal file
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from litescope.common import *
class LiteScopeIO(Module, AutoCSR):
def __init__(self, dw):
self.dw = dw
self._r_i = CSRStatus(dw)
self._r_o = CSRStorage(dw)
self.i = self._r_i.status
self.o = self._r_o.storage

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misoclib/tools/litescope/frontend/la.py Normal file
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from litescope.common import *
from litescope.core.trigger import LiteScopeTrigger
from litescope.core.storage import LiteScopeSubSampler, LiteScopeRecorder, LiteScopeRunLengthEncoder
from mibuild.tools import write_to_file
class LiteScopeLA(Module, AutoCSR):
def __init__(self, layout, depth, clk_domain="sys",
with_input_buffer=False,
with_rle=False, rle_length=256,
with_subsampler=False):
self.layout = layout
self.data = Cat(*layout)
self.dw = flen(self.data)
if with_rle:
self.dw = max(self.dw, log2_int(rle_length))
self.dw += 1
self.depth = depth
self.clk_domain = clk_domain
self.with_rle = with_rle
self.rle_length = rle_length
self.with_input_buffer = with_input_buffer
self.with_subsampler = with_subsampler
self.sink = Sink(data_layout(self.dw))
self.comb += [
self.sink.stb.eq(1),
self.sink.data.eq(self.data)
]
self.submodules.trigger = trigger = LiteScopeTrigger(self.dw)
self.submodules.recorder = recorder = LiteScopeRecorder(self.dw, self.depth)
def do_finalize(self):
sink = self.sink
# insert Buffer on sink (optional, can be used to improve timings)
if self.with_input_buffer:
input_buffer = Buffer(self.sink.description)
if self.clk_domain is not "sys":
self.submodules += RenameClockDomains(input_buffer, clk_domain)
else:
self.submodules += input_buffer
self.comb += Record.connect(sink, intput_buffer.d)
sink = intput_buffer.q
# clock domain crossing (optional, required when capture_clk is not sys_clk)
# XXX : sys_clk must be faster than capture_clk, add Converter on data to remove this limitation
if self.clk_domain is not "sys":
self.submodules.fifo = AsyncFIFO(self.sink.description, 32)
self.submodules += RenameClockDomains(self.fifo, {"write": self.clk_domain, "read": "sys"})
self.comb += Record.connect(sink, self.fifo.sink)
sink = self.fifo.source
# connect trigger
self.comb += [
self.trigger.sink.stb.eq(sink.stb),
self.trigger.sink.data.eq(sink.data),
]
# insert subsampler (optional)
if self.with_subsampler:
self.submodules.subsampler = LiteScopeSubSampler(self.dw)
self.comb += Record.connect(sink, self.subsampler.sink)
sink = self.subsampler.source
# connect recorder
self.comb += Record.connect(self.trigger.source, self.recorder.trigger_sink)
if self.with_rle:
self.submodules.rle = LiteScopeRunLengthEncoder(self.dw, self.rle_length)
self.comb += [
Record.connect(sink, self.rle.sink),
Record.connect(self.rle.source, self.recorder.data_sink),
self.rle.external_enable.eq(self.recorder.post_hit)
]
else:
self.submodules.delay_buffer = Buffer(self.sink.description)
self.comb += [
Record.connect(sink, self.delay_buffer.d),
Record.connect(self.delay_buffer.q, self.recorder.data_sink)
]
def export(self, vns, filename):
def format_line(*args):
return ",".join(args) + "\n"
r = ""
r += format_line("config", "dw", str(self.dw))
r += format_line("config", "depth", str(self.depth))
r += format_line("config", "with_rle", str(int(self.with_rle)))
if not isinstance(self.layout, tuple):
self.layout = [self.layout]
for e in self.layout:
r += format_line("layout", vns.get_name(e), str(flen(e)))
write_to_file(filename, r)

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misoclib/tools/litescope/host/__init__.py Normal file
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misoclib/tools/litescope/host/driver/__init__.py Normal file
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misoclib/tools/litescope/host/driver/etherbone.py Normal file
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import socket
from litescope.host.driver.reg import *
from liteeth.test.model.etherbone import *
class LiteScopeEtherboneDriver:
def __init__(self, ip_address, udp_port=20000, addrmap=None, busword=8, debug=False):
self.ip_address = ip_address
self.udp_port = udp_port
self.debug = debug
self.tx_sock = None
self.rx_sock = None
self.regs = build_map(addrmap, busword, self.read, self.write)
def open(self):
self.tx_sock = socket.socket(socket.AF_INET, socket.SOCK_DGRAM)
self.rx_sock = socket.socket(socket.AF_INET, socket.SOCK_DGRAM)
self.rx_sock.bind(("", self.udp_port))
def close(self):
pass
def read(self, addr, burst_length=None, repeats=None):
def to_int(v):
return 1 if v is None else v
reads_addrs = []
for i in range(to_int(repeats)):
reads_addrs += [addr+4*j for j in range(to_int(burst_length))]
reads = EtherboneReads(base_ret_addr=0x1000, addrs=reads_addrs)
record = EtherboneRecord()
record.writes = None
record.reads = reads
record.bca = 0
record.rca = 0
record.rff = 0
record.cyc = 0
record.wca = 0
record.wff = 0
record.byte_enable = 0xf
record.wcount = 0
record.rcount = len(reads_addrs)
packet = EtherbonePacket()
packet.records = [record]
packet.encode()
self.tx_sock.sendto(bytes(packet), (self.ip_address, self.udp_port))
datas, addrs = self.rx_sock.recvfrom(8192)
packet = EtherbonePacket(datas)
packet.decode()
datas = packet.records.pop().writes.get_datas()
if self.debug:
for i, data in enumerate(datas):
print("RD %08X @ %08X" %(data, addr + 4*(i%to_int(burst_length))))
return datas
def write(self, addr, datas):
if not isinstance(datas, list):
datas = [datas]
writes_datas = [d for d in datas]
writes = EtherboneWrites(base_addr=addr, datas=writes_datas)
record = EtherboneRecord()
record.writes = writes
record.reads = None
record.bca = 0
record.rca = 0
record.rff = 0
record.cyc = 0
record.wca = 0
record.wff = 0
record.byte_enable = 0xf
record.wcount = len(writes_datas)
record.rcount = 0
packet = EtherbonePacket()
packet.records = [record]
packet.encode()
self.tx_sock.sendto(bytes(packet), (self.ip_address, self.udp_port))
if self.debug:
for i, data in enumerate(datas):
print("WR %08X @ %08X" %(data, addr + 4*i))

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misoclib/tools/litescope/host/driver/io.py Normal file
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class LiteScopeIODriver():
def __init__(self, regs, name):
self.regs = regs
self.name = name
self.build()
def build(self):
for key, value in self.regs.d.items():
if self.name in key:
key = key.replace(self.name +"_", "")
setattr(self, key, value)
def write(self, value):
self.o.write(value)
def read(self):
return self.i.read()

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misoclib/tools/litescope/host/driver/la.py Normal file
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import csv
from struct import *
from migen.fhdl.structure import *
from litescope.host.dump import *
from litescope.host.driver.truthtable import *
class LiteScopeLADriver():
def __init__(self, regs, name, config_csv=None, clk_freq=None, debug=False):
self.regs = regs
self.name = name
if config_csv is None:
self.config_csv = name + ".csv"
if clk_freq is None:
try:
self.clk_freq = regs.identifier_frequency.read()
except:
self.clk_freq = None
self.samplerate = self.clk_freq
else:
self.clk_freq = clk_freq
self.samplerate = clk_freq
self.debug = debug
self.get_config()
self.get_layout()
self.build()
self.data = Dat(self.dw)
def get_config(self):
csv_reader = csv.reader(open(self.config_csv), delimiter=',', quotechar='#')
for item in csv_reader:
t, n, v = item
if t == "config":
setattr(self, n, int(v))
def get_layout(self):
self.layout = []
csv_reader = csv.reader(open(self.config_csv), delimiter=',', quotechar='#')
for item in csv_reader:
t, n, v = item
if t == "layout":
self.layout.append((n, int(v)))
def build(self):
for key, value in self.regs.d.items():
if self.name == key[:len(self.name)]:
key = key.replace(self.name + "_", "")
setattr(self, key, value)
value = 1
for name, length in self.layout:
setattr(self, name + "_o", value)
value = value*(2**length)
value = 0
for name, length in self.layout:
setattr(self, name + "_m", (2**length-1) << value)
value += length
def configure_term(self, port, trigger=0, mask=0, cond=None):
if cond is not None:
for k, v in cond.items():
trigger |= getattr(self, k + "_o")*v
mask |= getattr(self, k + "_m")
t = getattr(self, "trigger_port{d}_trig".format(d=int(port)))
m = getattr(self, "trigger_port{d}_mask".format(d=int(port)))
t.write(trigger)
m.write(mask)
def configure_range_detector(self, port, low, high):
l = getattr(self, "trigger_port{d}_low".format(d=int(port)))
h = getattr(self, "trigger_port{d}_high".format(d=int(port)))
l.write(low)
h.write(high)
def configure_edge_detector(self, port, rising_mask, falling_mask, both_mask):
rm = getattr(self, "trigger_port{d}_rising_mask".format(d=int(port)))
fm = getattr(self, "trigger_port{d}_falling_mask".format(d=int(port)))
bm = getattr(self, "trigger_port{d}_both_mask".format(d=int(port)))
rm.write(rising_mask)
fm.write(falling_mask)
bm.write(both_mask)
def configure_sum(self, equation):
datas = gen_truth_table(equation)
for adr, dat in enumerate(datas):
self.trigger_sum_prog_adr.write(adr)
self.trigger_sum_prog_dat.write(dat)
self.trigger_sum_prog_we.write(1)
def configure_subsampler(self, n):
self.subsampler_value.write(n-1)
if self.clk_freq is not None:
self.samplerate = self.clk_freq//n
else:
self.samplerate = None
def configure_qualifier(self, v):
self.recorder_qualifier.write(v)
def configure_rle(self, v):
self.rle_enable.write(v)
def done(self):
return self.recorder_done.read()
def run(self, offset, length):
if self.debug:
print("running")
self.recorder_offset.write(offset)
self.recorder_length.write(length)
self.recorder_trigger.write(1)
def upload(self):
if self.debug:
print("uploading")
while self.recorder_source_stb.read():
self.data.append(self.recorder_source_data.read())
self.recorder_source_ack.write(1)
if self.with_rle:
if self.rle_enable.read():
self.data = self.data.decode_rle()
return self.data
def save(self, filename):
if self.debug:
print("saving to " + filename)
name, ext = os.path.splitext(filename)
if ext == ".vcd":
from litescope.host.dump.vcd import VCDDump
dump = VCDDump()
elif ext == ".csv":
from litescope.host.dump.csv import CSVDump
dump = CSVDump()
elif ext == ".py":
from litescope.host.dump.python import PythonDump
dump = PythonDump()
elif ext == ".sr":
from litescope.host.dump.sigrok import SigrokDump
if self.samplerate is None:
raise ValueError("Unable to automatically retrieve clk_freq, clk_freq parameter required")
dump = SigrokDump(samplerate=self.samplerate)
else:
raise NotImplementedError
dump.add_from_layout(self.layout, self.data)
dump.write(filename)

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misoclib/tools/litescope/host/driver/reg.py Normal file
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import csv
class MappedReg:
def __init__(self, readfn, writefn, name, addr, length, busword, mode):
self.readfn = readfn
self.writefn = writefn
self.addr = addr
self.length = length
self.busword = busword
self.mode = mode
def read(self, repeats=None):
if self.mode not in ["rw", "ro"]:
raise KeyError(name + "register not readable")
def to_int(v):
return 1 if v is None else v
read_datas = self.readfn(self.addr, burst_length=self.length, repeats=repeats)
datas = []
for i in range(to_int(repeats)):
data = 0
for j in range(self.length):
data = data << self.busword
data |= read_datas[i*self.length+j]
datas.append(data)
if repeats is None:
return datas[0]
else:
return datas
def write(self, value):
if self.mode not in ["rw", "wo"]:
raise KeyError(name + "register not writable")
datas = []
for i in range(self.length):
datas.append((value >> ((self.length-1-i)*self.busword)) & (2**self.busword-1))
self.writefn(self.addr, datas)
class MappedRegs:
def __init__(self, d):
self.d = d
def __getattr__(self, attr):
try:
return self.__dict__['d'][attr]
except KeyError:
pass
raise KeyError("No such register " + attr)
def build_map(addrmap, busword, readfn, writefn):
csv_reader = csv.reader(open(addrmap), delimiter=',', quotechar='#')
d = {}
for item in csv_reader:
name, addr, length, mode = item
addr = int(addr.replace("0x", ""), 16)
length = int(length)
d[name] = MappedReg(readfn, writefn, name, addr, length, busword, mode)
return MappedRegs(d)

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misoclib/tools/litescope/host/driver/truthtable.py Normal file
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import os
import re
import sys
def is_number(x):
try:
_ = float(x)
except ValueError:
return False
return True
def remove_numbers(seq):
return [x for x in seq if not is_number(x)]
def remove_duplicates(seq):
seen = set()
seen_add = seen.add
return [x for x in seq if x not in seen and not seen_add(x)]
def get_operands(s):
operands = re.findall("[A-z0-9_]+", s)
operands = remove_duplicates(operands)
operands = remove_numbers(operands)
return sorted(operands)
def gen_truth_table(s):
operands = get_operands(s)
width = len(operands)
stim = []
for i in range(width):
stim_op = []
for j in range(2**width):
stim_op.append((int(j/(2**i)))%2)
stim.append(stim_op)
truth_table = []
for i in range(2**width):
for j in range(width):
exec("%s = stim[j][i]" %operands[j])
truth_table.append(eval(s) != 0)
return truth_table
def main():
print(gen_truth_table("(A&B&C)|D"))
if __name__ == '__main__':
main()

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misoclib/tools/litescope/host/driver/uart.py Normal file
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import serial
from struct import *
from litescope.host.driver.reg import *
def write_b(uart, data):
uart.write(pack('B',data))
class LiteScopeUARTDriver:
cmds = {
"write" : 0x01,
"read" : 0x02
}
def __init__(self, port, baudrate=115200, addrmap=None, busword=8, debug=False):
self.port = port
self.baudrate = str(baudrate)
self.debug = debug
self.uart = serial.Serial(port, baudrate, timeout=0.25)
self.regs = build_map(addrmap, busword, self.read, self.write)
def open(self):
self.uart.flushOutput()
self.uart.close()
self.uart.open()
self.uart.flushInput()
try:
self.regs.uart2wb_sel.write(1)
except:
pass
def close(self):
try:
self.regs.uart2wb_sel.write(0)
except:
pass
self.uart.flushOutput()
self.uart.close()
def read(self, addr, burst_length=None, repeats=None):
datas = []
def to_int(v):
return 1 if v is None else v
for i in range(to_int(repeats)):
self.uart.flushInput()
write_b(self.uart, self.cmds["read"])
write_b(self.uart, burst_length)
write_b(self.uart, (addr//4 & 0xff000000) >> 24)
write_b(self.uart, (addr//4 & 0x00ff0000) >> 16)
write_b(self.uart, (addr//4 & 0x0000ff00) >> 8)
write_b(self.uart, (addr//4 & 0x000000ff))
for j in range(to_int(burst_length)):
data = 0
for k in range(4):
data = data << 8
data |= ord(self.uart.read())
if self.debug:
print("RD %08X @ %08X" %(data, (addr+j)*4))
datas.append(data)
return datas
def write(self, addr, data):
if isinstance(data, list):
burst_length = len(data)
else:
burst_length = 1
write_b(self.uart, self.cmds["write"])
write_b(self.uart, burst_length)
write_b(self.uart, (addr//4 & 0xff000000) >> 24)
write_b(self.uart, (addr//4 & 0x00ff0000) >> 16)
write_b(self.uart, (addr//4 & 0x0000ff00) >> 8)
write_b(self.uart, (addr//4 & 0x000000ff))
if isinstance(data, list):
for i in range(len(data)):
dat = data[i]
for j in range(4):
write_b(self.uart, (dat & 0xff000000) >> 24)
dat = dat << 8
if self.debug:
print("WR %08X @ %08X" %(data[i], (addr + i)*4))
else:
dat = data
for j in range(4):
write_b(self.uart, (dat & 0xff000000) >> 24)
dat = dat << 8
if self.debug:
print("WR %08X @ %08X" %(data, (addr * 4)))

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def dec2bin(d, nb=0):
if d=="x":
return "x"*nb
elif d==0:
b="0"
else:
b=""
while d!=0:
b="01"[d&1]+b
d=d>>1
return b.zfill(nb)
def get_bits(values, low, high=None):
r = []
if high is None:
high = low+1
for val in values:
t = (val >> low) & (2**(high-low)-1)
r.append(t)
return r
class Dat(list):
def __init__(self, width):
self.width = width
def __getitem__(self, key):
if isinstance(key, int):
return get_bits(self, key)
elif isinstance(key, slice):
if key.start != None:
start = key.start
else:
start = 0
if key.stop != None:
stop = key.stop
else:
stop = self.width
if stop > self.width:
stop = self.width
if key.step != None:
raise KeyError
return get_bits(self, start, stop)
else:
raise KeyError
def decode_rle(self):
datas = Dat(self.width-1)
last_data = 0
for data in self:
rle = data >> (self.width-1)
data = data & (2**(self.width-1)-1)
if rle:
for i in range(data):
datas.append(last_data)
else:
datas.append(data)
last_data = data
return datas
class Var:
def __init__(self, name, width, values=[], type="wire", default="x"):
self.type = type
self.width = width
self.name = name
self.val = default
self.values = values
self.vcd_id = None
def set_vcd_id(self, s):
self.vcd_id = s
def __len__(self):
return len(self.values)
def change(self, cnt):
r = ""
try :
if self.values[cnt+1] != self.val:
r += "b"
r += dec2bin(self.values[cnt+1], self.width)
r += " "
r += self.vcd_id
r += "\n"
return r
except :
return r
return r
class Dump:
def __init__(self):
self.vars = []
self.vcd_id = "!"
def add(self, var):
var.set_vcd_id(self.vcd_id)
self.vcd_id = chr(ord(self.vcd_id)+1)
self.vars.append(var)
def add_from_layout(self, layout, var):
i=0
for s, n in layout:
self.add(Var(s, n, var[i:i+n]))
i += n
def __len__(self):
l = 0
for var in self.vars:
l = max(len(var),l)
return l

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misoclib/tools/litescope/host/dump/csv.py Normal file
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from litescope.host.dump import *
class CSVDump(Dump):
def __init__(self, init_dump=None):
Dump.__init__(self)
if init_dump:
self.vars = init_dump.vars
def generate_vars(self):
r = ""
for var in self.vars:
r += var.name
r += ","
r += "\n"
for var in self.vars:
r += str(var.width)
r += ","
r += "\n"
return r
def generate_dumpvars(self):
r = ""
for i in range(len(self)):
for var in self.vars:
try:
var.val = var.values[i]
except:
pass
if var.val == "x":
r += "x"
else:
r += dec2bin(var.val, var.width)
r += ", "
r+= "\n"
return r
def write(self, filename):
f = open(filename, "w")
f.write(self.generate_vars())
f.write(self.generate_dumpvars())
f.close()
def read(self, filename):
raise NotImplementedError("CSV files can not (yet) be read, please contribute!")
if __name__ == '__main__':
dump = CSVDump()
dump.add(Var("foo1", 1, [0,1,0,1,0,1]))
dump.add(Var("foo2", 2, [1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0]))
ramp = [i%128 for i in range(1024)]
dump.add(Var("ramp", 16, ramp))
dump.write("dump.csv")

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misoclib/tools/litescope/host/dump/python.py Normal file
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from litescope.host.dump import *
class PythonDump(Dump):
def __init__(self, init_dump=None):
Dump.__init__(self)
if init_dump:
self.vars = init_dump.vars
def generate_data(self):
r = "dump = {\n"
for var in self.vars:
r += "\"" + var.name + "\""
r += " : "
r += str(var.values)
r += ",\n"
r += "}"
return r
def write(self, filename):
f = open(filename, "w")
f.write(self.generate_data())
f.close()
def read(self, filename):
raise NotImplementedError("Python files can not (yet) be read, please contribute!")
if __name__ == '__main__':
dump = PythonDump()
dump.add(Var("foo1", 1, [0,1,0,1,0,1]))
dump.add(Var("foo2", 2, [1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0]))
ramp = [i%128 for i in range(1024)]
dump.add(Var("ramp", 16, ramp))
dump.write("dump.py")

149
misoclib/tools/litescope/host/dump/sigrok.py Normal file
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import os
import math
import shutil
import zipfile
import re
from collections import OrderedDict
from litescope.host.dump import *
class SigrokDump(Dump):
def __init__(self, init_dump=None, samplerate=50000000):
Dump.__init__(self)
if init_dump:
self.vars = init_dump.vars
self.samplerate = samplerate
def write_version(self):
f = open("version", "w")
f.write("1")
f.close()
def write_metadata(self, name):
f = open("metadata", "w")
r = """
[global]
sigrok version = 0.2.0
[device 1]
driver = litescope
capturefile = logic-1
unitsize = 1
total probes = {}
samplerate = {} KHz
""".format(
len(self.vars),
self.samplerate//1000,
)
for i, var in enumerate(self.vars):
r += "probe{} = {}\n".format(i+1, var.name)
f.write(r)
f.close()
def write_data(self):
# XXX are probes limited to 1 bit?
data_bits = math.ceil(len(self.vars)/8)*8
data_len = 0
for var in self.vars:
data_len = max(data_len, len(var))
datas = []
for i in range(data_len):
data = 0
for j, var in enumerate(reversed(self.vars)):
data = data << 1
try:
data |= var.values[i] %2
except:
pass
datas.append(data)
f = open("logic-1", "wb")
for data in datas:
f.write(data.to_bytes(data_bits//8, "big"))
f.close()
def zip(self, name):
f = zipfile.ZipFile(name + ".sr", "w")
os.chdir(name)
f.write("version")
f.write("metadata")
f.write("logic-1")
os.chdir("..")
f.close()
def write(self, filename):
name, ext = os.path.splitext(filename)
if os.path.exists(name):
shutil.rmtree(name)
os.makedirs(name)
os.chdir(name)
self.write_version()
self.write_metadata(name)
self.write_data()
os.chdir("..")
self.zip(name)
shutil.rmtree(name)
def unzip(self, filename, name):
f = open(filename, "rb")
z = zipfile.ZipFile(f)
if os.path.exists(name):
shutil.rmtree(name)
os.makedirs(name)
for file in z.namelist():
z.extract(file, name)
f.close()
def read_metadata(self):
probes = OrderedDict()
f = open("metadata", "r")
for l in f:
m = re.search("probe([0-9]+) = (\w+)", l, re.I)
if m is not None:
index = int(m.group(1))
name = m.group(2)
probes[name] = index
m = re.search("samplerate = ([0-9]+) kHz", l, re.I)
if m is not None:
self.samplerate = int(m.group(1))*1000
m = re.search("samplerate = ([0-9]+) mHz", l, re.I)
if m is not None:
self.samplerate = int(m.group(1))*1000000
f.close()
return probes
def read_data(self, name, nprobes):
datas = []
f = open("logic-1", "rb")
while True:
data = f.read(math.ceil(nprobes/8))
if data == bytes('', "utf-8"):
break
data = int.from_bytes(data, "big")
datas.append(data)
f.close()
return datas
def read(self, filename):
self.vars = []
name, ext = os.path.splitext(filename)
self.unzip(filename, name)
os.chdir(name)
probes = self.read_metadata()
datas = self.read_data(name, len(probes.keys()))
os.chdir("..")
shutil.rmtree(name)
for k, v in probes.items():
probe_data = []
for data in datas:
probe_data.append((data >> (v-1)) & 0x1)
self.add(Var(k, 1, probe_data))
if __name__ == '__main__':
dump = SigrokDump()
dump.add(Var("foo1", 1, [0,1,0,1,0,1]))
dump.add(Var("foo2", 2, [1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0]))
ramp = [i%128 for i in range(1024)]
dump.add(Var("ramp", 16, ramp))
dump.write("dump.sr")
dump.read("dump.sr")
dump.write("dump_copy.sr")

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misoclib/tools/litescope/host/dump/vcd.py Normal file
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import datetime
from litescope.host.dump import *
class VCDDump(Dump):
def __init__(self, init_dump=None, timescale="1ps", comment=""):
Dump.__init__(self)
if init_dump:
self.vars = init_dump.vars
self.timescale = timescale
self.comment = comment
self.cnt = -1
def change(self):
r = ""
c = ""
for var in self.vars:
c += var.change(self.cnt)
if c != "":
r += "#"
r += str(self.cnt+1)
r += "\n"
r += c
return r
def generate_date(self):
now = datetime.datetime.now()
r = "$date\n"
r += "\t"
r += now.strftime("%Y-%m-%d %H:%M")
r += "\n"
r += "$end\n"
return r
def generate_version(self):
r = "$version\n"
r += "\tmiscope VCD dump\n"
r += "$end\n"
return r
def generate_comment(self):
r = "$comment\n"
r += self.comment
r += "\n$end\n"
return r
def generate_timescale(self):
r = "$timescale "
r += self.timescale
r += " $end\n"
return r
def generate_scope(self):
r = "$scope "
r += self.timescale
r += " $end\n"
return r
def generate_vars(self):
r = ""
for var in self.vars:
r += "$var "
r += var.type
r += " "
r += str(var.width)
r += " "
r += var.vcd_id
r += " "
r += var.name
r += " $end\n"
return r
def generate_unscope(self):
r = "$unscope "
r += " $end\n"
return r
def generate_enddefinitions(self):
r = "$enddefinitions "
r += " $end\n"
return r
def generate_dumpvars(self):
r = "$dumpvars\n"
for var in self.vars:
r += "b"
r += dec2bin(var.val, var.width)
r += " "
r += var.vcd_id
r+= "\n"
r += "$end\n"
return r
def generate_valuechange(self):
r = ""
for i in range(len(self)):
r += self.change()
self.cnt += 1
return r
def __repr__(self):
r = ""
return r
def write(self, filename):
f = open(filename, "w")
f.write(self.generate_date())
f.write(self.generate_comment())
f.write(self.generate_timescale())
f.write(self.generate_scope())
f.write(self.generate_vars())
f.write(self.generate_unscope())
f.write(self.generate_enddefinitions())
f.write(self.generate_dumpvars())
f.write(self.generate_valuechange())
f.close()
def read(self, filename):
raise NotImplementedError("VCD files can not (yet) be read, please contribute!")
if __name__ == '__main__':
dump = VCDDump()
dump.add(Var("foo1", 1, [0,1,0,1,0,1]))
dump.add(Var("foo2", 2, [1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0]))
ramp = [i%128 for i in range(1024)]
dump.add(Var("ramp", 16, ramp))
dump.write("dump.vcd")

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#!/usr/bin/env python3
import sys, os, argparse, subprocess, struct, importlib
from mibuild.tools import write_to_file
from migen.util.misc import autotype
from migen.fhdl import verilog, edif
from migen.fhdl.structure import _Fragment
from migen.bank.description import CSRStatus
from mibuild import tools
from mibuild.xilinx_common import *
from litescope.common import *
def get_csr_csv(regions):
r = ""
for name, origin, busword, obj in regions:
if not isinstance(obj, Memory):
for csr in obj:
nr = (csr.size + busword - 1)//busword
r += "{}_{},0x{:08x},{},{}\n".format(name, csr.name, origin, nr, "ro" if isinstance(csr, CSRStatus) else "rw")
origin += 4*nr
return r
def _import(default, name):
return importlib.import_module(default + "." + name)
def _get_args():
parser = argparse.ArgumentParser(formatter_class=argparse.RawDescriptionHelpFormatter,
description="""\
LiteScope - based on Migen.
This program builds and/or loads LiteScope components.
One or several actions can be specified:
clean delete previous build(s).
build-rtl build verilog rtl.
build-bitstream build-bitstream build FPGA bitstream.
build-csr-csv save CSR map into CSV file.
load-bitstream load bitstream into volatile storage.
all clean, build-csr-csv, build-bitstream, load-bitstream.
""")
parser.add_argument("-t", "--target", default="simple", help="Core type to build")
parser.add_argument("-s", "--sub-target", default="", help="variant of the Core type to build")
parser.add_argument("-p", "--platform", default=None, help="platform to build for")
parser.add_argument("-Ot", "--target-option", default=[], nargs=2, action="append", help="set target-specific option")
parser.add_argument("-Op", "--platform-option", default=[], nargs=2, action="append", help="set platform-specific option")
parser.add_argument("--csr_csv", default="./test/csr.csv", help="CSV file to save the CSR map into")
parser.add_argument("action", nargs="+", help="specify an action")
return parser.parse_args()
# Note: misoclib need to be installed as a python library
if __name__ == "__main__":
args = _get_args()
# create top-level Core object
target_module = _import("targets", args.target)
if args.sub_target:
top_class = getattr(target_module, args.sub_target)
else:
top_class = target_module.default_subtarget
if args.platform is None:
platform_name = top_class.default_platform
else:
platform_name = args.platform
platform_module = _import("mibuild.platforms", platform_name)
platform_kwargs = dict((k, autotype(v)) for k, v in args.platform_option)
platform = platform_module.Platform(**platform_kwargs)
build_name = top_class.__name__.lower() + "-" + platform_name
top_kwargs = dict((k, autotype(v)) for k, v in args.target_option)
soc = top_class(platform, **top_kwargs)
soc.finalize()
# decode actions
action_list = ["clean", "build-csr-csv", "build-bitstream", "load-bitstream", "all"]
actions = {k: False for k in action_list}
for action in args.action:
if action in actions:
actions[action] = True
else:
print("Unknown action: "+action+". Valid actions are:")
for a in action_list:
print(" "+a)
sys.exit(1)
print("""
__ _ __ ____
/ / (_) /____ / __/______ ___ ___
/ /__/ / __/ -_)\ \/ __/ _ \/ _ \/ -_)
/____/_/\__/\__/___/\__/\___/ .__/\__/
/_/
A small footprint and configurable embedded FPGA
logic analyzer core powered by Migen
====== Building parameters: ======
LiscopeIO
---------
Width: {}
LiscopeLA
---------
Width: {}
Depth: {}
Subsampler: {}
RLE: {}
===============================""".format(
soc.io.dw,
soc.la.dw,
soc.la.depth,
str(soc.la.with_subsampler),
str(soc.la.with_rle)
)
)
# dependencies
if actions["all"]:
actions["build-csr-csv"] = True
actions["build-bitstream"] = True
actions["load-bitstream"] = True
if actions["build-bitstream"]:
actions["build-csr-csv"] = True
actions["build-bitstream"] = True
actions["load-bitstream"] = True
if actions["clean"]:
subprocess.call(["rm", "-rf", "build/*"])
if actions["build-csr-csv"]:
csr_csv = get_csr_csv(soc.cpu_csr_regions)
write_to_file(args.csr_csv, csr_csv)
if actions["build-bitstream"]:
vns = platform.build(soc, build_name=build_name, run=True)
if hasattr(soc, "do_exit") and vns is not None:
if hasattr(soc.do_exit, '__call__'):
soc.do_exit(vns)
if actions["load-bitstream"]:
prog = platform.create_programmer()
prog.load_bitstream("build/" + build_name + platform.bitstream_ext)

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#!/usr/bin/env python3
import sys, os
from setuptools import setup
from setuptools import find_packages
here = os.path.abspath(os.path.dirname(__file__))
README = open(os.path.join(here, "README")).read()
required_version = (3, 3)
if sys.version_info < required_version:
raise SystemExit("LiteScope requires python {0} or greater".format(
".".join(map(str, required_version))))
setup(
name="litescope",
version="unknown",
description="small footprint and configurable embedded FPGA logic analyzer",
long_description=README,
author="Florent Kermarrec",
author_email="florent@enjoy-digital.fr",
url="http://enjoy-digital.fr",
download_url="https://github.com/Florent-Kermarrec/litescope",
packages=find_packages(here),
license="GPL",
platforms=["Any"],
keywords="HDL ASIC FPGA hardware design",
classifiers=[
"Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)",
"Environment :: Console",
"Development Status :: Alpha",
"Intended Audience :: Developers",
"License :: OSI Approved :: GNU General Public License (GPL)",
"Operating System :: OS Independent",
"Programming Language :: Python",
],
)

26
misoclib/tools/targets/__init__.py Normal file
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import subprocess
from migen.fhdl.std import *
from migen.bank.description import *
def get_id():
output = subprocess.check_output(["git", "rev-parse", "HEAD"]).decode("ascii")
return int(output[:8], 16)
class Identifier(Module, AutoCSR):
def __init__(self, sysid, frequency, revision=None):
self._r_sysid = CSRStatus(16)
self._r_revision = CSRStatus(32)
self._r_frequency = CSRStatus(32)
###
if revision is None:
revision = get_id()
self.comb += [
self._r_sysid.status.eq(sysid),
self._r_revision.status.eq(revision),
self._r_frequency.status.eq(frequency),
]

109
misoclib/tools/targets/simple.py Normal file
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import os
from migen.bank import csrgen
from migen.bus import wishbone, csr
from migen.bus import wishbone2csr
from migen.bank.description import *
from targets import *
from litescope.common import *
from litescope.bridge.uart2wb import LiteScopeUART2WB
from litescope.frontend.io import LiteScopeIO
from litescope.frontend.la import LiteScopeLA
from litescope.core.port import LiteScopeTerm
class _CRG(Module):
def __init__(self, clk_in):
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_por = ClockDomain(reset_less=True)
# Power on Reset (vendor agnostic)
rst_n = Signal()
self.sync.por += rst_n.eq(1)
self.comb += [
self.cd_sys.clk.eq(clk_in),
self.cd_por.clk.eq(clk_in),
self.cd_sys.rst.eq(~rst_n)
]
class GenSoC(Module):
csr_base = 0x00000000
csr_data_width = 32
csr_map = {
"bridge": 0,
"identifier": 1,
}
interrupt_map = {}
cpu_type = None
def __init__(self, platform, clk_freq):
self.clk_freq = clk_freq
# UART <--> Wishbone bridge
self.submodules.uart2wb = LiteScopeUART2WB(platform.request("serial"), clk_freq, baud=115200)
# CSR bridge 0x00000000 (shadow @0x00000000)
self.submodules.wishbone2csr = wishbone2csr.WB2CSR(bus_csr=csr.Interface(self.csr_data_width))
self._wb_masters = [self.uart2wb.wishbone]
self._wb_slaves = [(lambda a: a[23:25] == 0, self.wishbone2csr.wishbone)]
self.cpu_csr_regions = [] # list of (name, origin, busword, csr_list/Memory)
# CSR
self.submodules.identifier = Identifier(0, int(clk_freq))
def add_cpu_memory_region(self, name, origin, length):
self.cpu_memory_regions.append((name, origin, length))
def add_cpu_csr_region(self, name, origin, busword, obj):
self.cpu_csr_regions.append((name, origin, busword, obj))
def do_finalize(self):
# Wishbone
self.submodules.wishbonecon = wishbone.InterconnectShared(self._wb_masters,
self._wb_slaves, register=True)
# CSR
self.submodules.csrbankarray = csrgen.BankArray(self,
lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override],
data_width=self.csr_data_width)
self.submodules.csrcon = csr.Interconnect(self.wishbone2csr.csr, self.csrbankarray.get_buses())
for name, csrs, mapaddr, rmap in self.csrbankarray.banks:
self.add_cpu_csr_region(name, 0xe0000000+0x800*mapaddr, flen(rmap.bus.dat_w), csrs)
for name, memory, mapaddr, mmap in self.csrbankarray.srams:
self.add_cpu_csr_region(name, 0xe0000000+0x800*mapaddr, flen(rmap.bus.dat_w), memory)
class LiteScopeSoC(GenSoC, AutoCSR):
default_platform = "de0nano"
csr_map = {
"io": 10,
"la": 11
}
csr_map.update(GenSoC.csr_map)
def __init__(self, platform):
clk_freq = 50*1000000
GenSoC.__init__(self, platform, clk_freq)
self.submodules.crg = _CRG(platform.request("clk50"))
self.submodules.io = LiteScopeIO(8)
self.leds = Cat(*[platform.request("user_led", i) for i in range(8)])
self.comb += self.leds.eq(self.io.o)
self.submodules.counter0 = counter0 = Counter(bits_sign=8)
self.submodules.counter1 = counter1 = Counter(bits_sign=8)
self.comb += [
counter0.ce.eq(1),
If(counter0.value == 16,
counter0.reset.eq(1),
counter1.ce.eq(1)
)
]
self.debug = (
counter1.value
)
self.submodules.la = LiteScopeLA(self.debug, 512, with_rle=True, with_subsampler=True)
self.la.trigger.add_port(LiteScopeTerm(self.la.dw))
def do_exit(self, vns):
self.la.export(vns, "test/la.csv")
default_subtarget = LiteScopeSoC

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misoclib/tools/test/Makefile Normal file
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LSDIR = ../
PYTHON = python3
CMD = PYTHONPATH=$(LSDIR) $(PYTHON)
test_regs:
$(CMD) test_regs.py
test_io:
$(CMD) test_io.py
test_la:
$(CMD) test_la.py

33
misoclib/tools/test/make.py Normal file
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#!/usr/bin/env python3
import argparse, importlib
def _get_args():
parser = argparse.ArgumentParser()
parser.add_argument("-b", "--bridge", default="uart", help="Bridge to use")
parser.add_argument("--port", default=3, help="UART port")
parser.add_argument("--baudrate", default=115200, help="UART baudrate")
parser.add_argument("--ip_address", default="192.168.1.40", help="Etherbone IP address")
parser.add_argument("--udp_port", default=20000, help="Etherbone UDP port")
parser.add_argument("--busword", default=32, help="CSR busword")
parser.add_argument("test", nargs="+", help="specify a test")
return parser.parse_args()
if __name__ == "__main__":
args = _get_args()
if args.bridge == "uart":
from litescope.host.driver.uart import LiteScopeUARTDriver
wb = LiteScopeUARTDriver(args.port, args.baudrate, "./csr.csv", int(args.busword), debug=False)
elif args.bridge == "etherbone":
from litescope.host.driver.etherbone import LiteScopeEtherboneDriver
wb = LiteScopeEtherboneDriver(args.ip_address, int(args.udp_port), "./csr.csv", int(args.busword), debug=False)
else:
ValueError("Invalid bridge {}".format(args.bridge))
def _import(name):
return importlib.import_module(name)
for test in args.test:
t = _import("test_"+test)
t.main(wb)

34
misoclib/tools/test/test_io.py Normal file
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import time
from litescope.host.driver.io import LiteScopeIODriver
def led_anim0(io):
for i in range(10):
io.write(0xA5)
time.sleep(0.1)
io.write(0x5A)
time.sleep(0.1)
def led_anim1(io):
for j in range(4):
#Led <<
led_data = 1
for i in range(8):
io.write(led_data)
time.sleep(i*i*0.0020)
led_data = (led_data<<1)
#Led >>
ledData = 128
for i in range(8):
io.write(led_data)
time.sleep(i*i*0.0020)
led_data = (led_data>>1)
def main(wb):
io = LiteScopeIODriver(wb.regs, "io")
wb.open()
###
led_anim0(io)
led_anim1(io)
print("%02X" %io.read())
###
wb.close()

26
misoclib/tools/test/test_la.py Normal file
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from litescope.host.driver.la import LiteScopeLADriver
def main(wb):
wb.open()
###
la = LiteScopeLADriver(wb.regs, "la", debug=True)
#cond = {"cnt0" : 128} # trigger on cnt0 = 128
cond = {} # trigger on cnt0 = 128
la.configure_term(port=0, cond=cond)
la.configure_sum("term")
la.configure_subsampler(1)
#la.configure_qualifier(1)
la.configure_rle(1)
la.run(offset=128, length=256)
while not la.done():
pass
la.upload()
la.save("dump.vcd")
la.save("dump.csv")
la.save("dump.py")
la.save("dump.sr")
###
wb.close()

9
misoclib/tools/test/test_regs.py Normal file
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def main(wb):
wb.open()
regs = wb.regs
###
print("sysid : 0x%04x" %regs.identifier_sysid.read())
print("revision : 0x%04x" %regs.identifier_revision.read())
print("frequency : %d MHz" %(regs.identifier_frequency.read()/1000000))
###
wb.close()