Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

revert simulation design and add wave

This commit is contained in:
Florent Kermarrec 2014-09-30 11:04:36 +02:00
parent 110580eb2e
commit b284819d18
4 changed files with 38 additions and 48 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Makefile
View File

@ -7,7 +7,7 @@ PLATFORM = kc705_impact
CMD = $(PYTHON) make.py -X $(CURDIR) -Op toolchain $(TOOLCHAIN) -p $(PLATFORM) -t test
csv:
cd $(MSCDIR) && $(CMD) --csr_csv $(CURDIR)/test/csr.csv build-csr-csv -Ot gen_mila_csv True
cd $(MSCDIR) && $(CMD) --csr_csv $(CURDIR)/test/csr.csv build-csr-csv
cd $(CURDIR)
bit:

BIN
sim/sim.png Normal file
View File

Binary file not shown.
Side by Side

After

Width:  |  Height:  |  Size: 24 KiB

32
sim/wave.do Normal file
View File

@ -0,0 +1,32 @@
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -radix hexadecimal /top_tb/dut/sataphy_host_source_payload_d
add wave -noupdate /top_tb/dut/sataphy_host_source_stb
add wave -noupdate -radix hexadecimal /top_tb/dut/sataphy_device_source_payload_d
add wave -noupdate -radix hexadecimal /top_tb/dut/sataphy_device_source_stb
add wave -noupdate -radix hexadecimal /top_tb/refclk_p
add wave -noupdate -radix hexadecimal /top_tb/refclk_n
add wave -noupdate -radix hexadecimal /top_tb/clk200_p
add wave -noupdate -radix hexadecimal /top_tb/clk200_n
add wave -noupdate -radix hexadecimal /top_tb/sata_txp
add wave -noupdate -radix hexadecimal /top_tb/sata_txn
add wave -noupdate -radix hexadecimal /top_tb/sata_rxp
add wave -noupdate -radix hexadecimal /top_tb/sata_rxn
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {16623348 ps} 0} {{Cursor 2} {21767465 ps} 0}
quietly wave cursor active 1
configure wave -namecolwidth 446
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ps
update
WaveRestoreZoom {0 ps} {17730427 ps}

52
targets/test.py
View File

@ -88,63 +88,21 @@ class UART2WB(Module):
class TestDesign(UART2WB):
default_platform = "kc705"
csr_map = {
"mila": 10
}
csr_map.update(UART2WB.csr_map)
def __init__(self, platform, **kwargs):
def __init__(self, platform):
clk_freq = 166666*1000
UART2WB.__init__(self, platform, clk_freq)
self.submodules.crg = _CRG(platform)
self.submodules.sataphy_host = K7SATAPHY(platform.request("sata_host"), clk_freq,
host=True, default_speed="SATA3")
self.submodules.sataphy_host = K7SATAPHY(platform.request("sata_host"), clk_freq, host=True)
self.comb += [
self.sataphy_host.sink.stb.eq(1),
self.sataphy_host.sink.payload.d.eq(0x12345678)
]
import os
from miscope import trigger, miio, mila
from mibuild.tools import write_to_file
from migen.fhdl import verilog
term = trigger.Term(width=64)
self.submodules.mila = mila.MiLa(width=64, depth=2048, ports=[term], with_rle=True)
gtx = self.sataphy_host.gtx
ctrl = self.sataphy_host.ctrl
mila_dat = (
gtx.rxresetdone,
gtx.txresetdone,
gtx.rxuserrdy,
gtx.txuserrdy,
gtx.rxcominitdet,
gtx.rxcomwakedet,
gtx.txcomfinish,
gtx.txcominit,
gtx.txcomwake,
)
self.submodules.sataphy_device = K7SATAPHY(platform.request("sata_device"), clk_freq, host=False)
self.comb += [
self.mila.sink.stb.eq(1),
self.mila.sink.dat.eq(Cat(*mila_dat))
self.sataphy_device.sink.stb.eq(1),
self.sataphy_device.sink.payload.d.eq(0x12345678)
]
try:
gen_mila_csv = kwargs.pop('gen_mila_csv')
except:
gen_mila_csv = False
if gen_mila_csv:
r, ns = verilog.convert(self, return_ns=True)
mila_csv = self.mila.get_csv(mila_dat, ns)
write_to_file(os.path.join(platform.soc_ext_path, "test", "mila.csv"), mila_csv)
default_subtarget = TestDesign