uart/software: remove litescope dependency

This commit is contained in:
Florent Kermarrec 2015-09-21 09:04:59 +02:00
parent bc1450e4f2
commit b2a4eead0c
2 changed files with 56 additions and 1 deletions

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@ -0,0 +1,55 @@
import csv
class MappedReg:
def __init__(self, readfn, writefn, name, addr, length, busword, mode):
self.readfn = readfn
self.writefn = writefn
self.addr = addr
self.length = length
self.busword = busword
self.mode = mode
def read(self):
if self.mode not in ["rw", "ro"]:
raise KeyError(name + "register not readable")
datas = self.readfn(self.addr, burst_length=self.length)
if isinstance(datas, int):
return datas
else:
data = 0
for i in range(self.length):
data = data << self.busword
data |= datas[i]
return data
def write(self, value):
if self.mode not in ["rw", "wo"]:
raise KeyError(name + "register not writable")
datas = []
for i in range(self.length):
datas.append((value >> ((self.length-1-i)*self.busword)) & (2**self.busword-1))
self.writefn(self.addr, datas)
class MappedRegs:
def __init__(self, d):
self.d = d
def __getattr__(self, attr):
try:
return self.__dict__['d'][attr]
except KeyError:
pass
raise KeyError("No such register " + attr)
def build_map(addrmap, busword, readfn, writefn):
csv_reader = csv.reader(open(addrmap), delimiter=',', quotechar='#')
d = {}
for item in csv_reader:
name, addr, length, mode = item
addr = int(addr.replace("0x", ""), 16)
length = int(length)
d[name] = MappedReg(readfn, writefn, name, addr, length, busword, mode)
return MappedRegs(d)

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@ -1,6 +1,6 @@
import serial import serial
from struct import * from struct import *
from misoclib.tools.litescope.software.driver.reg import * from misoclib.com.uart.software.reg import *
def write_b(uart, data): def write_b(uart, data):