soc: avoid double definition of main_ram

2020-02-11 16:39:37 +01:00 · 2020-02-11 16:39:37 +01:00 · b2c66b1efd
parent 5f9946085b
commit b2c66b1efd
1 changed files with 1 additions and 1 deletions
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@ -958,7 +958,7 @@ class LiteXSoC(SoC):
        elif self.with_wishbone:
            # Wishbone Slave SDRAM interface -------------------------------------------------------
            wb_sdram = wishbone.Interface()
-            self.bus.add_slave("main_ram", wb_sdram, SoCRegion(origin=origin, size=sdram_size))
+            self.bus.add_slave("main_ram", wb_sdram)

            # L2 Cache -----------------------------------------------------------------------------
            if l2_cache_size != 0: