Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

soc: avoid double definition of main_ram

This commit is contained in:
Florent Kermarrec 2020-02-11 16:39:37 +01:00
parent 5f9946085b
commit b2c66b1efd
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
litex/soc/integration/soc.py
View File

@ -958,7 +958,7 @@ class LiteXSoC(SoC):
elif self.with_wishbone: elif self.with_wishbone:
# Wishbone Slave SDRAM interface ------------------------------------------------------- # Wishbone Slave SDRAM interface -------------------------------------------------------
wb_sdram = wishbone.Interface() wb_sdram = wishbone.Interface()
self.bus.add_slave("main_ram", wb_sdram, SoCRegion(origin=origin, size=sdram_size)) self.bus.add_slave("main_ram", wb_sdram)
# L2 Cache ----------------------------------------------------------------------------- # L2 Cache -----------------------------------------------------------------------------
if l2_cache_size != 0: if l2_cache_size != 0: