sdram: create frontend dir and move dma_lasmi/memtest/wishbone2lasmi to it

misoclib/com/liteusb/frontend/dma.py

@@ -1,11 +1,13 @@
 from migen.fhdl.std import *
 from migen.flow.actor import *
 from migen.flow.network import *
-from migen.actorlib import dma_lasmi, structuring, spi
+from migen.actorlib import structuring, spi
 from migen.bank.description import *
 from migen.bank.eventmanager import *
 from migen.genlib.record import Record
 
+from misoclib.mem.sdram.frontend import dma_lasmi
+
 from liteusb.ftdi.std import *
 
 class FtdiDMAWriter(Module, AutoCSR):

misoclib/mem/sdram/frontend/dma_lasmi.py

@@ -0,0 +1,89 @@
+from migen.fhdl.std import *
+from migen.flow.actor import *
+from migen.genlib.fifo import SyncFIFO
+
+class Reader(Module):
+	def __init__(self, lasmim, fifo_depth=None):
+		self.address = Sink([("a", lasmim.aw)])
+		self.data = Source([("d", lasmim.dw)])
+		self.busy = Signal()
+
+		###
+
+		if fifo_depth is None:
+			fifo_depth = lasmim.req_queue_size + lasmim.read_latency + 2
+
+		# request issuance
+		request_enable = Signal()
+		request_issued = Signal()
+
+		self.comb += [
+			lasmim.we.eq(0),
+			lasmim.stb.eq(self.address.stb & request_enable),
+			lasmim.adr.eq(self.address.a),
+			self.address.ack.eq(lasmim.req_ack & request_enable),
+			request_issued.eq(lasmim.stb & lasmim.req_ack)
+		]
+
+		# FIFO reservation level counter
+		# incremented when data is planned to be queued
+		# decremented when data is dequeued
+		data_dequeued = Signal()
+		rsv_level = Signal(max=fifo_depth+1)
+		self.sync += [
+			If(request_issued,
+				If(~data_dequeued, rsv_level.eq(rsv_level + 1))
+			).Elif(data_dequeued,
+				rsv_level.eq(rsv_level - 1)
+			)
+		]
+		self.comb += [
+			self.busy.eq(rsv_level != 0),
+			request_enable.eq(rsv_level != fifo_depth)
+		]
+
+		# FIFO
+		fifo = SyncFIFO(lasmim.dw, fifo_depth)
+		self.submodules += fifo
+
+		self.comb += [
+			fifo.din.eq(lasmim.dat_r),
+			fifo.we.eq(lasmim.dat_r_ack),
+
+			self.data.stb.eq(fifo.readable),
+			fifo.re.eq(self.data.ack),
+			self.data.d.eq(fifo.dout),
+			data_dequeued.eq(self.data.stb & self.data.ack)
+		]
+
+
+class Writer(Module):
+	def __init__(self, lasmim, fifo_depth=None):
+		self.address_data = Sink([("a", lasmim.aw), ("d", lasmim.dw)])
+		self.busy = Signal()
+
+		###
+
+		if fifo_depth is None:
+			fifo_depth = lasmim.req_queue_size + lasmim.write_latency + 2
+
+		fifo = SyncFIFO(lasmim.dw, fifo_depth)
+		self.submodules += fifo
+
+		self.comb += [
+			lasmim.we.eq(1),
+			lasmim.stb.eq(fifo.writable & self.address_data.stb),
+			lasmim.adr.eq(self.address_data.a),
+			self.address_data.ack.eq(fifo.writable & lasmim.req_ack),
+			fifo.we.eq(self.address_data.stb & lasmim.req_ack),
+			fifo.din.eq(self.address_data.d)
+		]
+
+		self.comb += [
+			fifo.re.eq(lasmim.dat_w_ack),
+			If(data_valid,
+				lasmim.dat_we.eq(2**(lasmim.dw//8)-1),
+				lasmim.dat_w.eq(fifo.dout)
+			),
+			self.busy.eq(fifo.readable)
+		]

misoclib/mem/sdram/frontend/memtest.py

@@ -1,9 +1,10 @@
 from migen.fhdl.std import *
 from migen.genlib.misc import optree
 from migen.bank.description import *
-from migen.actorlib import dma_lasmi
 from migen.actorlib.spi import *
 
+from misoclib.mem.sdram.frontend import dma_lasmi
+
 @DecorateModule(InsertReset)
 @DecorateModule(InsertCE)
 class LFSR(Module):

misoclib/mem/sdram/lasmicon/test/lasmicon_df.py

@@ -1,9 +1,9 @@
 from migen.fhdl.std import *
-from migen.actorlib import dma_lasmi
 from migen.sim.generic import run_simulation
 
 from misoclib.mem.sdram.bus import lasmibus
 from misoclib.mem.sdram.lasmicon import *
+from misoclib.mem.sdram.frontend import dma_lasmi
 
 from common import sdram_phy, sdram_geom, sdram_timing, DFILogger
 

misoclib/mem/sdram/lasmicon/test/lasmicon_wb.py

@@ -3,8 +3,9 @@ from migen.bus import wishbone
 from migen.bus.transactions import *
 from migen.sim.generic import run_simulation
 
-from misoclib.mem.sdram.bus import lasmibus, wishbone2lasmi
+from misoclib.mem.sdram.bus import lasmibus
 from misoclib.mem.sdram.lasmicon import *
+from misoclib.mem.sdram.frontend import wishbone2lasmi
 
 from common import sdram_phy, sdram_geom, sdram_timing, DFILogger
 

misoclib/soc/sdram.py

@@ -1,10 +1,10 @@
 from migen.fhdl.std import *
 from migen.bus import wishbone, csr
 
-from misoclib.mem.sdram.bus import dfi, lasmibus, wishbone2lasmi
+from misoclib.mem.sdram.bus import dfi, lasmibus
 from misoclib.mem.sdram import minicon, lasmicon
 from misoclib.mem.sdram import dfii
-from misoclib.mem.sdram import memtest
+from misoclib.mem.sdram.frontend import memtest, wishbone2lasmi
 from misoclib.soc import SoC, mem_decoder
 
 class SDRAMSoC(SoC):

misoclib/video/dvisampler/debug.py

@@ -2,8 +2,9 @@ from migen.fhdl.std import *
 from migen.genlib.fifo import AsyncFIFO
 from migen.genlib.record import layout_len
 from migen.bank.description import AutoCSR
-from migen.actorlib import structuring, dma_lasmi, spi
+from migen.actorlib import structuring, spi
 
+from misoclib.mem.sdram.frontend import dma_lasmi
 from misoclib.video.dvisampler.edid import EDID
 from misoclib.video.dvisampler.clocking import Clocking
 from misoclib.video.dvisampler.datacapture import DataCapture

misoclib/video/dvisampler/dma.py

@@ -3,7 +3,8 @@ from migen.genlib.fsm import FSM, NextState
 from migen.bank.description import *
 from migen.bank.eventmanager import *
 from migen.flow.actor import *
-from migen.actorlib import dma_lasmi
+
+from misoclib.mem.sdram.frontend import dma_lasmi
 
 # Slot status: EMPTY=0 LOADED=1 PENDING=2
 class _Slot(Module, AutoCSR):

misoclib/video/framebuffer/__init__.py

@@ -2,8 +2,9 @@ from migen.fhdl.std import *
 from migen.flow.network import *
 from migen.flow import plumbing
 from migen.bank.description import AutoCSR
-from migen.actorlib import dma_lasmi, structuring, misc
+from migen.actorlib import structuring, misc
 
+from misoclib.mem.sdram.frontend import dma_lasmi
 from misoclib.video.framebuffer.format import bpp, pixel_layout, FrameInitiator, VTG
 from misoclib.video.framebuffer.phy import Driver