liteeth: create example design derived from SoC that can be used on all targets with Ethernet pins
This commit is contained in:
Florent Kermarrec
parent
b34be816ec
commit
b32a0e6f9e
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@ -51,17 +51,20 @@ if __name__ == "__main__":
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args = _get_args()
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# create top-level Core object
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target_module = _import("misoclib.com.liteeth.example_designs.targets", args.target)
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target_module = _import("targets", args.target)
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if args.sub_target:
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top_class = getattr(target_module, args.sub_target)
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else:
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top_class = target_module.default_subtarget
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if args.platform is None:
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platform_name = top_class.default_platform
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if hasattr(top_class, "default_platform"):
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platform_name = top_class.default_platform
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else:
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raise ValueError("Target has no default platform, specify a platform with -p your_platform")
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else:
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platform_name = args.platform
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platform_module = _import("misoclib.com.liteeth.example_designs.platforms", platform_name)
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platform_module = _import("mibuild.platforms", platform_name)
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platform_kwargs = dict((k, autotype(v)) for k, v in args.platform_option)
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platform = platform_module.Platform(**platform_kwargs)
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@ -1,112 +0,0 @@
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from mibuild.generic_platform import *
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from mibuild.crg import SimpleCRG
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from mibuild.xilinx.common import CRG_DS
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from mibuild.xilinx.ise import XilinxISEPlatform
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from mibuild.xilinx.vivado import XilinxVivadoPlatform
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from mibuild.xilinx.programmer import *
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_io = [
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("user_led", 0, Pins("AB8"), IOStandard("LVCMOS15")),
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("user_led", 1, Pins("AA8"), IOStandard("LVCMOS15")),
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("user_led", 2, Pins("AC9"), IOStandard("LVCMOS15")),
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("user_led", 3, Pins("AB9"), IOStandard("LVCMOS15")),
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("user_led", 4, Pins("AE26"), IOStandard("LVCMOS25")),
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("user_led", 5, Pins("G19"), IOStandard("LVCMOS25")),
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("user_led", 6, Pins("E18"), IOStandard("LVCMOS25")),
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("user_led", 7, Pins("F16"), IOStandard("LVCMOS25")),
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("cpu_reset", 0, Pins("AB7"), IOStandard("LVCMOS15")),
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("clk200", 0,
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Subsignal("p", Pins("AD12"), IOStandard("LVDS")),
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Subsignal("n", Pins("AD11"), IOStandard("LVDS"))
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),
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("clk156", 0,
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Subsignal("p", Pins("K28"), IOStandard("LVDS_25")),
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Subsignal("n", Pins("K29"), IOStandard("LVDS_25"))
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),
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("serial", 0,
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Subsignal("cts", Pins("L27")),
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Subsignal("rts", Pins("K23")),
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Subsignal("tx", Pins("K24")),
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Subsignal("rx", Pins("M19")),
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IOStandard("LVCMOS25")
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),
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("eth_clocks", 0,
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Subsignal("tx", Pins("M28")),
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Subsignal("gtx", Pins("K30")),
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Subsignal("rx", Pins("U27")),
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IOStandard("LVCMOS25")
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),
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("eth", 0,
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Subsignal("rst_n", Pins("L20")),
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Subsignal("int_n", Pins("N30")),
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Subsignal("mdio", Pins("J21")),
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Subsignal("mdc", Pins("R23")),
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Subsignal("dv", Pins("R28")),
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Subsignal("rx_er", Pins("V26")),
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Subsignal("rx_data", Pins("U30 U25 T25 U28 R19 T27 T26 T28")),
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Subsignal("tx_en", Pins("M27")),
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Subsignal("tx_er", Pins("N29")),
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Subsignal("tx_data", Pins("N27 N25 M29 L28 J26 K26 L30 J28")),
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Subsignal("col", Pins("W19")),
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Subsignal("crs", Pins("R30")),
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IOStandard("LVCMOS25")
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),
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]
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def Platform(*args, toolchain="vivado", programmer="xc3sprog", **kwargs):
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if toolchain == "ise":
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xilinx_platform = XilinxISEPlatform
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elif toolchain == "vivado":
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xilinx_platform = XilinxVivadoPlatform
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else:
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raise ValueError
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class RealPlatform(xilinx_platform):
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bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g ConfigRate:12 -g SPI_buswidth:4"
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def __init__(self, crg_factory=lambda p: CRG_DS(p, "clk200", "cpu_reset")):
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xilinx_platform.__init__(self, "xc7k325t-ffg900-2", _io, crg_factory)
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def create_programmer(self):
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if programmer == "xc3sprog":
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return XC3SProg("jtaghs1_fast", "bscan_spi_kc705.bit")
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elif programmer == "vivado":
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return VivadoProgrammer()
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else:
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raise ValueError
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def do_finalize(self, fragment):
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try:
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self.add_period_constraint(self.lookup_request("clk156").p, 6.4)
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except ConstraintError:
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pass
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try:
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self.add_period_constraint(self.lookup_request("clk200").p, 5.0)
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except ConstraintError:
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pass
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try:
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self.add_period_constraint(self.lookup_request("eth_clocks").rx, 8.0)
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except ConstraintError:
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pass
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self.add_platform_command("""
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create_clock -name sys_clk -period 6 [get_nets sys_clk]
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create_clock -name eth_rx_clk -period 8 [get_nets eth_rx_clk]
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create_clock -name eth_tx_clk -period 8 [get_nets eth_tx_clk]
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set_false_path -from [get_clocks sys_clk] -to [get_clocks eth_rx_clk]
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set_false_path -from [get_clocks sys_clk] -to [get_clocks eth_tx_clk]
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set_false_path -from [get_clocks eth_rx_clk] -to [get_clocks sys_clk]
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set_false_path -from [get_clocks eth_tx_clk] -to [get_clocks sys_clk]
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 2.5 [current_design]
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""")
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return RealPlatform(*args, **kwargs)
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@ -1,14 +1,7 @@
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import os
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from migen.bank import csrgen
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from migen.bus import wishbone, csr
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from migen.bus import wishbone2csr
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from migen.genlib.cdc import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from migen.bus import wishbone
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from migen.bank.description import *
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from targets import *
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from misoclib.soc import SoC
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from misoclib.tools.litescope.common import *
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from misoclib.tools.litescope.bridge.uart2wb import LiteScopeUART2WB
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from misoclib.tools.litescope.frontend.la import LiteScopeLA
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@ -20,97 +13,20 @@ from misoclib.com.liteeth.phy.gmii import LiteEthPHYGMII
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from misoclib.com.liteeth.core import LiteEthUDPIPCore
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class _CRG(Module):
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def __init__(self, platform):
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def __init__(self, clk_in):
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self.clock_domains.cd_sys = ClockDomain()
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self.reset = Signal()
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self.clock_domains.cd_por = ClockDomain(reset_less=True)
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clk200 = platform.request("clk200")
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clk200_se = Signal()
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self.specials += Instance("IBUFDS", i_I=clk200.p, i_IB=clk200.n, o_O=clk200_se)
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pll_locked = Signal()
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pll_fb = Signal()
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pll_sys = Signal()
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self.specials += [
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Instance("PLLE2_BASE",
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p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
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# VCO @ 1GHz
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p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=5.0,
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p_CLKFBOUT_MULT=5, p_DIVCLK_DIVIDE=1,
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i_CLKIN1=clk200_se, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb,
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# 166MHz
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p_CLKOUT0_DIVIDE=6, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=pll_sys,
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p_CLKOUT1_DIVIDE=2, p_CLKOUT1_PHASE=0.0, #o_CLKOUT1=,
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p_CLKOUT2_DIVIDE=2, p_CLKOUT2_PHASE=0.0, #o_CLKOUT2=,
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p_CLKOUT3_DIVIDE=2, p_CLKOUT3_PHASE=0.0, #o_CLKOUT3=,
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p_CLKOUT4_DIVIDE=2, p_CLKOUT4_PHASE=0.0, #o_CLKOUT4=
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),
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Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk),
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AsyncResetSynchronizer(self.cd_sys, ~pll_locked | platform.request("cpu_reset") | self.reset),
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# Power on Reset (vendor agnostic)
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rst_n = Signal()
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self.sync.por += rst_n.eq(1)
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self.comb += [
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self.cd_sys.clk.eq(clk_in),
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self.cd_por.clk.eq(clk_in),
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self.cd_sys.rst.eq(~rst_n)
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]
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class SoC(Module):
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csr_base = 0x00000000
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csr_data_width = 32
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csr_map = {
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"bridge": 0,
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"identifier": 1,
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}
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interrupt_map = {}
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cpu_type = None
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def __init__(self, platform, clk_freq):
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self.clk_freq = clk_freq
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# UART <--> Wishbone bridge
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self.submodules.bridge = LiteScopeUART2WB(platform.request("serial"), clk_freq, baud=921600)
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# CSR bridge 0x00000000 (shadow @0x00000000)
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self.submodules.wishbone2csr = wishbone2csr.WB2CSR(bus_csr=csr.Interface(self.csr_data_width))
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self._wb_masters = [self.bridge.wishbone]
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self._wb_slaves = [(lambda a: a[23:25] == 0, self.wishbone2csr.wishbone)]
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self.cpu_csr_regions = [] # list of (name, origin, busword, csr_list/Memory)
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# CSR
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self.submodules.identifier = Identifier(0, int(clk_freq), 0)
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def add_wb_master(self, wbm):
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if self.finalized:
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raise FinalizeError
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self._wb_masters.append(wbm)
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def add_wb_slave(self, address_decoder, interface):
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if self.finalized:
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raise FinalizeError
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self._wb_slaves.append((address_decoder, interface))
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def add_cpu_memory_region(self, name, origin, length):
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self.cpu_memory_regions.append((name, origin, length))
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def add_cpu_csr_region(self, name, origin, busword, obj):
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self.cpu_csr_regions.append((name, origin, busword, obj))
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def do_finalize(self):
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# Wishbone
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self.submodules.wishbonecon = wishbone.InterconnectShared(self._wb_masters,
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self._wb_slaves, register=True)
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# CSR
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self.submodules.csrbankarray = csrgen.BankArray(self,
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lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override],
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data_width=self.csr_data_width)
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self.submodules.csrcon = csr.Interconnect(self.wishbone2csr.csr, self.csrbankarray.get_buses())
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for name, csrs, mapaddr, rmap in self.csrbankarray.banks:
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self.add_cpu_csr_region(name, 0xe0000000+0x800*mapaddr, flen(rmap.bus.dat_w), csrs)
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for name, memory, mapaddr, mmap in self.csrbankarray.srams:
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self.add_cpu_csr_region(name, 0xe0000000+0x800*mapaddr, flen(rmap.bus.dat_w), memory)
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class BaseSoC(SoC, AutoCSR):
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default_platform = "kc705"
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csr_map = {
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"phy": 11,
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"core": 12
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@ -119,8 +35,17 @@ class BaseSoC(SoC, AutoCSR):
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def __init__(self, platform, clk_freq=166*1000000,
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mac_address=0x10e2d5000000,
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ip_address="192.168.1.40"):
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SoC.__init__(self, platform, clk_freq)
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self.submodules.crg = _CRG(platform)
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clk_freq = int((1/(platform.default_clk_period))*1000000000)
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self.submodules.uart2wb = LiteScopeUART2WB(platform.request("serial"), clk_freq, baud=115200)
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SoC.__init__(self, platform, clk_freq, self.uart2wb,
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with_cpu=False,
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with_csr=True, csr_data_width=32,
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with_uart=False,
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with_identifier=True,
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with_timer=False
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)
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clk_in = platform.request(platform.default_clk_name)
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self.submodules.crg = _CRG(clk_in if not hasattr(clk_in, "p") else clk_in.p)
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# wishbone SRAM (to test Wishbone over UART and Etherbone)
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self.submodules.sram = wishbone.SRAM(1024)
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@ -37,7 +37,8 @@ class LiteScopeSoC(SoC, AutoCSR):
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with_identifier=True,
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with_timer=False
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)
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self.submodules.crg = _CRG(platform.request(platform.default_clk_name))
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clk_in = platform.request(platform.default_clk_name)
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self.submodules.crg = _CRG(clk_in if not hasattr(clk_in, "p") else clk_in.p)
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self.submodules.io = LiteScopeIO(8)
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for i in range(8):
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@ -24,6 +24,7 @@ class SimpleSoC(SoC):
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with_rom=True,
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with_sdram=True, sdram_size=16*1024,
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**kwargs)
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self.submodules.crg = _CRG(platform.request(platform.default_clk_name))
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clk_in = platform.request(platform.default_clk_name)
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self.submodules.crg = _CRG(clk_in if not hasattr(clk_in, "p") else clk_in.p)
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default_subtarget = SimpleSoC
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