cores/cpu/microwatt: fix non irq variant, add standard+irq/"standard+gdhl+irq variants, move XICSSlave after CPU class.
This commit is contained in:
Florent Kermarrec
parent
3673f38d63
commit
b3a42d76ce
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@ -17,7 +17,196 @@ from litex.gen.common import reverse_bytes
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from litex.soc.cores.cpu import CPU
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CPU_VARIANTS = ["standard", "standard+ghdl"]
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CPU_VARIANTS = ["standard", "standard+ghdl", "standard+irq", "standard+ghdl+irq"]
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class Microwatt(CPU):
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name = "microwatt"
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human_name = "Microwatt"
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variants = CPU_VARIANTS
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data_width = 64
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endianness = "little"
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gcc_triple = ("powerpc64le-linux", "powerpc64le-linux-gnu")
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linker_output_format = "elf64-powerpcle"
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nop = "nop"
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io_regions = {0xc0000000: 0x10000000} # origin, length
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@property
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def mem_map(self):
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return {"csr": 0xc0000000}
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@property
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def gcc_flags(self):
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flags = "-m64 "
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flags += "-mabi=elfv2 "
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flags += "-msoft-float "
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flags += "-mno-string "
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flags += "-mno-multiple "
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flags += "-mno-vsx "
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flags += "-mno-altivec "
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flags += "-mlittle-endian "
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flags += "-mstrict-align "
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flags += "-fno-stack-protector "
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flags += "-mcmodel=small "
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flags += "-D__microwatt__ "
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return flags
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def __init__(self, platform, variant="standard"):
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self.platform = platform
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self.variant = variant
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self.reset = Signal()
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self.wb_insn = wb_insn = wishbone.Interface(data_width=64, adr_width=29)
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self.wb_data = wb_data = wishbone.Interface(data_width=64, adr_width=29)
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self.periph_buses = [wb_insn, wb_data]
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self.memory_buses = []
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if "irq" in variant:
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self.interrupt = Signal(16)
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self.core_ext_irq = Signal()
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# # #
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self.cpu_params = dict(
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# Clock / Reset
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i_clk = ClockSignal(),
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i_rst = ResetSignal() | self.reset,
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# Wishbone instruction bus
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i_wishbone_insn_dat_r = wb_insn.dat_r,
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i_wishbone_insn_ack = wb_insn.ack,
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i_wishbone_insn_stall = wb_insn.cyc & ~wb_insn.ack, # No burst support
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o_wishbone_insn_adr = Cat(Signal(3), wb_insn.adr),
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o_wishbone_insn_dat_w = wb_insn.dat_w,
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o_wishbone_insn_cyc = wb_insn.cyc,
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o_wishbone_insn_stb = wb_insn.stb,
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o_wishbone_insn_sel = wb_insn.sel,
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o_wishbone_insn_we = wb_insn.we,
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# Wishbone data bus
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i_wishbone_data_dat_r = wb_data.dat_r,
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i_wishbone_data_ack = wb_data.ack,
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i_wishbone_data_stall = wb_data.cyc & ~wb_data.ack, # No burst support
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o_wishbone_data_adr = Cat(Signal(3), wb_data.adr),
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o_wishbone_data_dat_w = wb_data.dat_w,
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o_wishbone_data_cyc = wb_data.cyc,
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o_wishbone_data_stb = wb_data.stb,
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o_wishbone_data_sel = wb_data.sel,
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o_wishbone_data_we = wb_data.we,
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# Debug bus
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i_dmi_addr = 0,
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i_dmi_din = 0,
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#o_dmi_dout =,
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i_dmi_req = 0,
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i_dmi_wr = 0,
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#o_dmi_ack =,
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# Interrupt controller
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i_core_ext_irq = self.core_ext_irq,
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)
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# add vhdl sources
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self.add_sources(platform, use_ghdl_yosys_plugin="ghdl" in self.variant)
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# add XICS controller
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if "irq" in variant:
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self.add_xics()
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def set_reset_address(self, reset_address):
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assert not hasattr(self, "reset_address")
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self.reset_address = reset_address
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assert reset_address == 0x00000000
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def add_xics(self):
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self.submodules.xics = XICSSlave(
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platform = self.platform,
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variant = self.variant,
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core_irq_out = self.core_ext_irq,
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int_level_in = self.interrupt,
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endianness = self.endianness
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)
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@staticmethod
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def add_sources(platform, use_ghdl_yosys_plugin=False):
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sources = [
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# Common / Types / Helpers
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"decode_types.vhdl",
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"wishbone_types.vhdl",
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"utils.vhdl",
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"common.vhdl",
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"helpers.vhdl",
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# Fetch
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"fetch1.vhdl",
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"fetch2.vhdl",
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# Instruction/Data Cache
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"cache_ram.vhdl",
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"plru.vhdl",
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"dcache.vhdl",
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"icache.vhdl",
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# Decode
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"insn_helpers.vhdl",
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"decode1.vhdl",
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"gpr_hazard.vhdl",
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"cr_hazard.vhdl",
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"control.vhdl",
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"decode2.vhdl",
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# Register/CR File
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"register_file.vhdl",
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"crhelpers.vhdl",
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"cr_file.vhdl",
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# Execute
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"ppc_fx_insns.vhdl",
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"logical.vhdl",
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"rotator.vhdl",
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"countzero.vhdl",
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"execute1.vhdl",
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# Load/Store
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"loadstore1.vhdl",
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# Multiply/Divide
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"multiply.vhdl",
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"divider.vhdl",
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# Writeback
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"writeback.vhdl",
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# MMU
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"mmu.vhdl",
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# Core
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"core_debug.vhdl",
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"core.vhdl",
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]
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sdir = get_data_mod("cpu", "microwatt").data_location
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cdir = os.path.dirname(__file__)
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if use_ghdl_yosys_plugin:
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from litex.build import tools
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import subprocess
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ys = []
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ys.append("ghdl --ieee=synopsys -fexplicit -frelaxed-rules --std=08 \\")
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for source in sources:
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ys.append(os.path.join(sdir, source) + " \\")
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ys.append(os.path.join(os.path.dirname(__file__), "microwatt_wrapper.vhdl") + " \\")
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ys.append("-e microwatt_wrapper")
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ys.append("chformal -assert -remove")
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ys.append("write_verilog {}".format(os.path.join(cdir, "microwatt.v")))
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tools.write_to_file(os.path.join(cdir, "microwatt.ys"), "\n".join(ys))
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if subprocess.call(["yosys", "-q", "-m", "ghdl", os.path.join(cdir, "microwatt.ys")]):
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raise OSError("Unable to convert Microwatt CPU to verilog, please check your GHDL-Yosys-plugin install")
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platform.add_source(os.path.join(cdir, "microwatt.v"))
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else:
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platform.add_sources(sdir, *sources)
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platform.add_source(os.path.join(os.path.dirname(__file__), "microwatt_wrapper.vhdl"))
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def do_finalize(self):
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self.specials += Instance("microwatt_wrapper", **self.cpu_params)
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class XICSSlave(Module, AutoCSR):
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def __init__(self, platform, core_irq_out=Signal(), int_level_in=Signal(16), endianness="big", variant="standard"):
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@ -140,188 +329,3 @@ class XICSSlave(Module, AutoCSR):
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def do_finalize(self):
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self.specials += Instance("xics_icp_wrapper", **self.icp_params)
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self.specials += Instance("xics_ics_wrapper", **self.ics_params)
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class Microwatt(CPU):
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name = "microwatt"
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human_name = "Microwatt"
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variants = CPU_VARIANTS
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data_width = 64
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endianness = "little"
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gcc_triple = ("powerpc64le-linux", "powerpc64le-linux-gnu")
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linker_output_format = "elf64-powerpcle"
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nop = "nop"
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io_regions = {0xc0000000: 0x10000000} # origin, length
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@property
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def mem_map(self):
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return {"csr": 0xc0000000}
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@property
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def gcc_flags(self):
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flags = "-m64 "
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flags += "-mabi=elfv2 "
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flags += "-msoft-float "
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flags += "-mno-string "
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flags += "-mno-multiple "
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flags += "-mno-vsx "
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flags += "-mno-altivec "
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flags += "-mlittle-endian "
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flags += "-mstrict-align "
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flags += "-fno-stack-protector "
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flags += "-mcmodel=small "
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flags += "-D__microwatt__ "
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return flags
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def __init__(self, platform, variant="standard"):
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self.platform = platform
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self.variant = variant
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self.reset = Signal()
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self.wb_insn = wb_insn = wishbone.Interface(data_width=64, adr_width=29)
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self.wb_data = wb_data = wishbone.Interface(data_width=64, adr_width=29)
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self.periph_buses = [wb_insn, wb_data]
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self.memory_buses = []
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self.interrupt = Signal(16)
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self.core_ext_irq = Signal()
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# # #
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self.cpu_params = dict(
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# Clock / Reset
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i_clk = ClockSignal(),
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i_rst = ResetSignal() | self.reset,
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# Wishbone instruction bus
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i_wishbone_insn_dat_r = wb_insn.dat_r,
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i_wishbone_insn_ack = wb_insn.ack,
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i_wishbone_insn_stall = wb_insn.cyc & ~wb_insn.ack, # No burst support
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o_wishbone_insn_adr = Cat(Signal(3), wb_insn.adr),
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o_wishbone_insn_dat_w = wb_insn.dat_w,
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o_wishbone_insn_cyc = wb_insn.cyc,
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o_wishbone_insn_stb = wb_insn.stb,
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o_wishbone_insn_sel = wb_insn.sel,
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o_wishbone_insn_we = wb_insn.we,
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# Wishbone data bus
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i_wishbone_data_dat_r = wb_data.dat_r,
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i_wishbone_data_ack = wb_data.ack,
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i_wishbone_data_stall = wb_data.cyc & ~wb_data.ack, # No burst support
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o_wishbone_data_adr = Cat(Signal(3), wb_data.adr),
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o_wishbone_data_dat_w = wb_data.dat_w,
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o_wishbone_data_cyc = wb_data.cyc,
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o_wishbone_data_stb = wb_data.stb,
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o_wishbone_data_sel = wb_data.sel,
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o_wishbone_data_we = wb_data.we,
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# Debug bus
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i_dmi_addr = 0,
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i_dmi_din = 0,
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#o_dmi_dout =,
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i_dmi_req = 0,
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i_dmi_wr = 0,
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#o_dmi_ack =,
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# Interrupt controller
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i_core_ext_irq = self.core_ext_irq,
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)
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# add vhdl sources
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self.add_sources(platform, use_ghdl_yosys_plugin="ghdl" in self.variant)
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# add XICS controller
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self.add_xics()
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def set_reset_address(self, reset_address):
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assert not hasattr(self, "reset_address")
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self.reset_address = reset_address
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assert reset_address == 0x00000000
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def add_xics(self):
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self.submodules.xics = XICSSlave(
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platform = self.platform,
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variant = self.variant,
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core_irq_out = self.core_ext_irq,
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int_level_in = self.interrupt,
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endianness = self.endianness)
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@staticmethod
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def add_sources(platform, use_ghdl_yosys_plugin=False):
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sources = [
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# Common / Types / Helpers
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"decode_types.vhdl",
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"wishbone_types.vhdl",
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"utils.vhdl",
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"common.vhdl",
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"helpers.vhdl",
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# Fetch
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"fetch1.vhdl",
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"fetch2.vhdl",
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# Instruction/Data Cache
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"cache_ram.vhdl",
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"plru.vhdl",
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"dcache.vhdl",
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"icache.vhdl",
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# Decode
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"insn_helpers.vhdl",
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"decode1.vhdl",
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"gpr_hazard.vhdl",
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"cr_hazard.vhdl",
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"control.vhdl",
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"decode2.vhdl",
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# Register/CR File
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"register_file.vhdl",
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"crhelpers.vhdl",
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"cr_file.vhdl",
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# Execute
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"ppc_fx_insns.vhdl",
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"logical.vhdl",
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"rotator.vhdl",
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"countzero.vhdl",
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"execute1.vhdl",
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# Load/Store
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"loadstore1.vhdl",
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# Multiply/Divide
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"multiply.vhdl",
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"divider.vhdl",
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# Writeback
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"writeback.vhdl",
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# MMU
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"mmu.vhdl",
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# Core
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"core_debug.vhdl",
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"core.vhdl",
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]
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sdir = get_data_mod("cpu", "microwatt").data_location
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cdir = os.path.dirname(__file__)
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if use_ghdl_yosys_plugin:
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from litex.build import tools
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import subprocess
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ys = []
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ys.append("ghdl --ieee=synopsys -fexplicit -frelaxed-rules --std=08 \\")
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for source in sources:
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ys.append(os.path.join(sdir, source) + " \\")
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ys.append(os.path.join(os.path.dirname(__file__), "microwatt_wrapper.vhdl") + " \\")
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ys.append("-e microwatt_wrapper")
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ys.append("chformal -assert -remove")
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ys.append("write_verilog {}".format(os.path.join(cdir, "microwatt.v")))
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tools.write_to_file(os.path.join(cdir, "microwatt.ys"), "\n".join(ys))
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if subprocess.call(["yosys", "-q", "-m", "ghdl", os.path.join(cdir, "microwatt.ys")]):
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raise OSError("Unable to convert Microwatt CPU to verilog, please check your GHDL-Yosys-plugin install")
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platform.add_source(os.path.join(cdir, "microwatt.v"))
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else:
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platform.add_sources(sdir, *sources)
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platform.add_source(os.path.join(os.path.dirname(__file__), "microwatt_wrapper.vhdl"))
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def do_finalize(self):
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self.specials += Instance("microwatt_wrapper", **self.cpu_params)
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@ -12,6 +12,8 @@ extern "C" {
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#include <generated/soc.h>
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#include <generated/mem.h>
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#ifdef CONFIG_CPU_HAS_INTERRUPT
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// Address of exception / IRQ handler routine
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extern void * __rom_isr_address;
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void isr(uint64_t vec);
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@ -154,6 +156,9 @@ static inline unsigned int irq_pending(void)
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return pending;
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}
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#endif /* CONFIG_CPU_HAS_INTERRUPT */
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#ifdef __cplusplus
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}
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#endif
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