examples/../top: update
This commit is contained in:
Florent Kermarrec
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@ -7,23 +7,23 @@
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#
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# Copyright 2012 / Florent Kermarrec / florent@enjoy-digital.fr
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#
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# migScope Example on De0 Nano Board
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# miscope Example on De0 Nano Board
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# ----------------------------------
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################################################################################
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#
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# In this example signals are generated in the FPGA.
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# We will use migScope to record those signals and visualize them.
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# We use miscope to record those signals and visualize them.
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#
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# Example architecture:
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# ----------------------
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# migScope Config --> Python Client (Host) --> Vcd Output
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# miscope Config --> Python Client (Host) --> Vcd Output
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# & Trig |
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# Arduino (Uart<-->Spi Bridge)
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# |
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# De0 Nano
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# |
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# +--------------------+-----------------------+
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# migIo Signal Generator migLa
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# miIo Signal Generator miLa
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# Control of Signal Ramp, Sinus, Logic Analyzer
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# generator Square, ...
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###############################################################################
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@ -39,10 +39,10 @@ from migen.bus.transactions import *
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from migen.bank import description, csrgen
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from migen.bank.description import *
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from miscope import trigger, recorder, miIo, miLa
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import sys
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sys.path.append("../../")
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from migScope import trigger, recorder, migIo, migLa
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import spi2Csr
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from timings import *
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@ -70,9 +70,9 @@ dat1_width = 32
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record_size = 4096
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# Csr Addr
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MIGIO0_ADDR = 0x0000
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MIGLA0_ADDR = 0x0200
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MIGLA1_ADDR = 0x0600
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MIIO0_ADDR = 0x0000
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MILA0_ADDR = 0x0200
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MILA1_ADDR = 0x0600
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#==============================================================================
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# M I S C O P E E X A M P L E
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@ -80,21 +80,21 @@ MIGLA1_ADDR = 0x0600
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def get():
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# migIo0
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migIo0 = migIo.MigIo(MIGIO0_ADDR, 8, "IO")
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miIo0 = miIo.MiIo(MIIO0_ADDR, 8, "IO")
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# migLa0
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term0 = trigger.Term(trig0_width)
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trigger0 = trigger.Trigger(trig0_width, [term0])
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recorder0 = recorder.Recorder(dat0_width, record_size)
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migLa0 = migLa.MigLa(MIGLA0_ADDR, trigger0, recorder0)
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miLa0 = miLa.MiLa(MILA0_ADDR, trigger0, recorder0)
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# migLa1
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term1 = trigger.Term(trig1_width)
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trigger1 = trigger.Trigger(trig1_width, [term1])
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recorder1 = recorder.Recorder(dat1_width, record_size)
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migLa1 = migLa.MigLa(MIGLA1_ADDR, trigger1, recorder1)
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miLa1 = miLa.MiLa(MILA1_ADDR, trigger1, recorder1)
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# Spi2Csr
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spi2csr0 = spi2Csr.Spi2Csr(16,8)
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@ -102,11 +102,11 @@ def get():
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# Csr Interconnect
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csrcon0 = csr.Interconnect(spi2csr0.csr,
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[
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migIo0.bank.bus,
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migLa0.trig.bank.bus,
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migLa0.rec.bank.bus,
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migLa1.trig.bank.bus,
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migLa1.rec.bank.bus,
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miIo0.bank.bus,
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miLa0.trig.bank.bus,
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miLa0.rec.bank.bus,
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miLa1.trig.bank.bus,
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miLa1.rec.bank.bus,
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])
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comb = []
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@ -147,11 +147,11 @@ def get():
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# Signal Selection
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sig_gen = Signal(8)
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comb += [
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If(migIo0.o == 0,
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If(miIo0.o == 0,
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sig_gen.eq(cnt_gen)
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).Elif(migIo0.o == 1,
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).Elif(miIo0.o == 1,
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sig_gen.eq(square_gen)
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).Elif(migIo0.o == 2,
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).Elif(miIo0.o == 2,
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sig_gen.eq(sinus_gen)
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).Else(
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sig_gen.eq(0)
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@ -160,23 +160,23 @@ def get():
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# Led
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led0 = Signal(8)
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comb += [led0.eq(migIo0.o[:8])]
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comb += [led0.eq(miIo0.o[:8])]
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# MigLa0 input
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comb += [
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migLa0.in_trig.eq(sig_gen),
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migLa0.in_dat.eq(sig_gen)
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miLa0.in_trig.eq(sig_gen),
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miLa0.in_dat.eq(sig_gen)
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]
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# MigLa1 input
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comb += [
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migLa1.in_trig[:8].eq(spi2csr0.csr.dat_w),
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migLa1.in_trig[8:24].eq(spi2csr0.csr.adr),
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migLa1.in_trig[24].eq(spi2csr0.csr.we),
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migLa1.in_dat[:8].eq(spi2csr0.csr.dat_w),
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migLa1.in_dat[8:24].eq(spi2csr0.csr.adr),
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migLa1.in_dat[24].eq(spi2csr0.csr.we)
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miLa1.in_trig[:8].eq(spi2csr0.csr.dat_w),
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miLa1.in_trig[8:24].eq(spi2csr0.csr.adr),
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miLa1.in_trig[24].eq(spi2csr0.csr.we),
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miLa1.in_dat[:8].eq(spi2csr0.csr.dat_w),
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miLa1.in_dat[8:24].eq(spi2csr0.csr.adr),
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miLa1.in_dat[24].eq(spi2csr0.csr.we)
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]
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@ -7,23 +7,23 @@
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#
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# Copyright 2012 / Florent Kermarrec / florent@enjoy-digital.fr
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#
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# migScope Example on De1 Board
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# miscope Example on De1 Board
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# ----------------------------------
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################################################################################
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#
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# In this example signals are generated in the FPGA.
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# We will use migScope to record those signals and visualize them.
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# We use miscope to record those signals and visualize them.
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#
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# Example architecture:
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# ----------------------
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# migScope Config --> Python Client (Host) --> Vcd Output
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# miscope Config --> Python Client (Host) --> Vcd Output
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# & Trig |
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# Arduino (Uart<-->Spi Bridge)
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# |
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# De1
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# |
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# +--------------------+-----------------------+
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# migIo Signal Generator migLa
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# miIo Signal Generator miLa
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# Control of Signal Ramp, Sinus, Logic Analyzer
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# generator Square, ...
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###############################################################################
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@ -39,10 +39,10 @@ from migen.bus.transactions import *
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from migen.bank import description, csrgen
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from migen.bank.description import *
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from miscope import trigger, recorder, miIo, miLa
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import sys
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sys.path.append("../../")
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from migScope import trigger, recorder, migIo, migLa
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import spi2Csr
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from timings import *
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@ -70,9 +70,9 @@ dat1_width = 32
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record_size = 4096
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# Csr Addr
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MIGIO0_ADDR = 0x0000
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MIGLA0_ADDR = 0x0200
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MIGLA1_ADDR = 0x0600
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MIIO0_ADDR = 0x0000
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MILA0_ADDR = 0x0200
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MILA1_ADDR = 0x0600
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#==============================================================================
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# M I S C O P E E X A M P L E
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@ -80,21 +80,21 @@ MIGLA1_ADDR = 0x0600
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def get():
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# migIo0
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migIo0 = migIo.MigIo(MIGIO0_ADDR, 8, "IO")
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miIo0 = miIo.MiIo(MIIO0_ADDR, 8, "IO")
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# migLa0
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term0 = trigger.Term(trig0_width)
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trigger0 = trigger.Trigger(trig0_width, [term0])
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recorder0 = recorder.Recorder(dat0_width, record_size)
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migLa0 = migLa.MigLa(MIGLA0_ADDR, trigger0, recorder0)
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miLa0 = miLa.MiLa(MILA0_ADDR, trigger0, recorder0)
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# migLa1
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term1 = trigger.Term(trig1_width)
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trigger1 = trigger.Trigger(trig1_width, [term1])
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recorder1 = recorder.Recorder(dat1_width, record_size)
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migLa1 = migLa.MigLa(MIGLA1_ADDR, trigger1, recorder1)
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miLa1 = miLa.MiLa(MILA1_ADDR, trigger1, recorder1)
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# Spi2Csr
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spi2csr0 = spi2Csr.Spi2Csr(16,8)
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@ -102,11 +102,11 @@ def get():
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# Csr Interconnect
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csrcon0 = csr.Interconnect(spi2csr0.csr,
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[
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migIo0.bank.bus,
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migLa0.trig.bank.bus,
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migLa0.rec.bank.bus,
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migLa1.trig.bank.bus,
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migLa1.rec.bank.bus,
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miIo0.bank.bus,
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miLa0.trig.bank.bus,
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miLa0.rec.bank.bus,
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miLa1.trig.bank.bus,
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miLa1.rec.bank.bus,
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])
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comb = []
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@ -147,11 +147,11 @@ def get():
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# Signal Selection
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sig_gen = Signal(8)
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comb += [
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If(migIo0.o == 0,
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If(miIo0.o == 0,
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sig_gen.eq(cnt_gen)
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).Elif(migIo0.o == 1,
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).Elif(miIo0.o == 1,
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sig_gen.eq(square_gen)
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).Elif(migIo0.o == 2,
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).Elif(miIo0.o == 2,
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sig_gen.eq(sinus_gen)
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).Else(
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sig_gen.eq(0)
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@ -160,26 +160,26 @@ def get():
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# Led
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led0 = Signal(8)
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comb += [led0.eq(migIo0.o[:8])]
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comb += [led0.eq(miIo0.o[:8])]
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#Switch
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sw0 = Signal(8)
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comb += [migIo0.i.eq(sw0)]
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comb += [miIo0.i.eq(sw0)]
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# MigLa0 input
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comb += [
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migLa0.in_trig.eq(sig_gen),
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migLa0.in_dat.eq(sig_gen)
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miLa0.in_trig.eq(sig_gen),
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miLa0.in_dat.eq(sig_gen)
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]
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# MigLa1 input
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comb += [
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migLa1.in_trig[:8].eq(spi2csr0.csr.dat_w),
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migLa1.in_trig[8:24].eq(spi2csr0.csr.adr),
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migLa1.in_trig[24].eq(spi2csr0.csr.we),
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migLa1.in_dat[:8].eq(spi2csr0.csr.dat_w),
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migLa1.in_dat[8:24].eq(spi2csr0.csr.adr),
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migLa1.in_dat[24].eq(spi2csr0.csr.we)
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miLa1.in_trig[:8].eq(spi2csr0.csr.dat_w),
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miLa1.in_trig[8:24].eq(spi2csr0.csr.adr),
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miLa1.in_trig[24].eq(spi2csr0.csr.we),
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miLa1.in_dat[:8].eq(spi2csr0.csr.dat_w),
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miLa1.in_dat[8:24].eq(spi2csr0.csr.adr),
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miLa1.in_dat[24].eq(spi2csr0.csr.we)
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]
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