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add option for BUFGCE to the clock generator buffer types

This commit is contained in:
bunnie 2020-01-24 14:58:51 +08:00
parent eae0e00496
commit b3f9aa11be
1 changed files with 3 additions and 1 deletions
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4
litex/soc/cores/clock.py
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@ -41,7 +41,7 @@ class XilinxClocking(Module, AutoCSR):
raise ValueError raise ValueError
self.clkin_freq = freq self.clkin_freq = freq
def create_clkout(self, cd, freq, phase=0, buf="bufg", margin=1e-2, with_reset=True): def create_clkout(self, cd, freq, phase=0, buf="bufg", margin=1e-2, with_reset=True, clk_ce=None):
assert self.nclkouts < self.nclkouts_max assert self.nclkouts < self.nclkouts_max
clkout = Signal() clkout = Signal()
self.clkouts[self.nclkouts] = (clkout, freq, phase, margin) self.clkouts[self.nclkouts] = (clkout, freq, phase, margin)
@ -57,6 +57,8 @@ class XilinxClocking(Module, AutoCSR):
self.specials += Instance("BUFG", i_I=clkout, o_O=clkout_buf) self.specials += Instance("BUFG", i_I=clkout, o_O=clkout_buf)
elif buf == "bufr": elif buf == "bufr":
self.specials += Instance("BUFR", i_I=clkout, o_O=clkout_buf) self.specials += Instance("BUFR", i_I=clkout, o_O=clkout_buf)
elif buf == "bufgce" and clk_ce != None:
self.specials += Instance("BUFGCE", i_I=clkout, o_O=clkout_buf, i_CE=clk_ce)
else: else:
raise ValueError raise ValueError