remove use of _r prefix on CSRs
This commit is contained in:
Florent Kermarrec
parent
696819cc7f
commit
b437dc3185
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@ -3,8 +3,8 @@ from misoclib.tools.litescope.common import *
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class LiteScopeIO(Module, AutoCSR):
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def __init__(self, dw):
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self.dw = dw
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self._r_i = CSRStatus(dw)
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self._r_o = CSRStorage(dw)
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self._i = CSRStatus(dw)
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self._o = CSRStorage(dw)
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self.i = self._r_i.status
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self.o = self._r_o.storage
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self.i = self._i.status
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self.o = self._o.storage
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@ -120,7 +120,7 @@ class FrameExtraction(Module, AutoCSR):
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self.frame = Source(word_layout)
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self.busy = Signal()
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self._r_overflow = CSR()
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self._overflow = CSR()
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###
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@ -194,11 +194,11 @@ class FrameExtraction(Module, AutoCSR):
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overflow_mask = Signal()
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self.comb += [
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self._r_overflow.w.eq(sys_overflow & ~overflow_mask),
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self.overflow_reset.i.eq(self._r_overflow.re)
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self._overflow.w.eq(sys_overflow & ~overflow_mask),
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self.overflow_reset.i.eq(self._overflow.re)
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]
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self.sync += \
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If(self._r_overflow.re,
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If(self._overflow.re,
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overflow_mask.eq(1)
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).Elif(self.overflow_reset_ack.o,
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overflow_mask.eq(0)
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@ -42,7 +42,7 @@ class ChanSync(Module, AutoCSR):
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self.valid_i = Signal()
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self.chan_synced = Signal()
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self._r_channels_synced = CSRStatus()
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self._channels_synced = CSRStatus()
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lst_control = []
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all_control = Signal()
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@ -85,7 +85,7 @@ class ChanSync(Module, AutoCSR):
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)
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)
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)
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self.specials += MultiReg(self.chan_synced, self._r_channels_synced.status)
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self.specials += MultiReg(self.chan_synced, self._channels_synced.status)
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class _TB(Module):
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def __init__(self, test_seq_it):
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@ -11,8 +11,8 @@ class CharSync(Module, AutoCSR):
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self.synced = Signal()
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self.data = Signal(10)
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self._r_char_synced = CSRStatus()
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self._r_ctl_pos = CSRStatus(bits_for(9))
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self._char_synced = CSRStatus()
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self._ctl_pos = CSRStatus(bits_for(9))
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###
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@ -47,7 +47,7 @@ class CharSync(Module, AutoCSR):
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),
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previous_control_position.eq(control_position)
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]
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self.specials += MultiReg(self.synced, self._r_char_synced.status)
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self.specials += MultiReg(word_sel, self._r_ctl_pos.status)
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self.specials += MultiReg(self.synced, self._char_synced.status)
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self.specials += MultiReg(word_sel, self._ctl_pos.status)
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self.sync.pix += self.data.eq(raw >> word_sel)
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@ -4,16 +4,16 @@ from migen.bank.description import *
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class Clocking(Module, AutoCSR):
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def __init__(self, pads):
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self._r_pll_reset = CSRStorage(reset=1)
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self._r_locked = CSRStatus()
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self._pll_reset = CSRStorage(reset=1)
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self._locked = CSRStatus()
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# DRP
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self._r_pll_adr = CSRStorage(5)
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self._r_pll_dat_r = CSRStatus(16)
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self._r_pll_dat_w = CSRStorage(16)
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self._r_pll_read = CSR()
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self._r_pll_write = CSR()
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self._r_pll_drdy = CSRStatus()
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self._pll_adr = CSRStorage(5)
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self._pll_dat_r = CSRStatus(16)
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self._pll_dat_w = CSRStorage(16)
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self._pll_read = CSR()
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self._pll_write = CSR()
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self._pll_drdy = CSRStatus()
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self.locked = Signal()
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self.serdesstrobe = Signal()
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@ -32,10 +32,10 @@ class Clocking(Module, AutoCSR):
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pll_clk1 = Signal()
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pll_clk2 = Signal()
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pll_drdy = Signal()
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self.sync += If(self._r_pll_read.re | self._r_pll_write.re,
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self._r_pll_drdy.status.eq(0)
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self.sync += If(self._pll_read.re | self._pll_write.re,
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self._pll_drdy.status.eq(0)
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).Elif(pll_drdy,
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self._r_pll_drdy.status.eq(1)
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self._pll_drdy.status.eq(1)
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)
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self.specials += Instance("PLL_ADV",
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p_CLKFBOUT_MULT=10,
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@ -48,13 +48,13 @@ class Clocking(Module, AutoCSR):
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i_CLKIN1=clk_se,
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o_CLKOUT0=pll_clk0, o_CLKOUT1=pll_clk1, o_CLKOUT2=pll_clk2,
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o_CLKFBOUT=clkfbout, i_CLKFBIN=clkfbout,
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o_LOCKED=pll_locked, i_RST=self._r_pll_reset.storage,
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o_LOCKED=pll_locked, i_RST=self._pll_reset.storage,
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i_DADDR=self._r_pll_adr.storage,
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o_DO=self._r_pll_dat_r.status,
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i_DI=self._r_pll_dat_w.storage,
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i_DEN=self._r_pll_read.re | self._r_pll_write.re,
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i_DWE=self._r_pll_write.re,
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i_DADDR=self._pll_adr.storage,
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o_DO=self._pll_dat_r.status,
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i_DI=self._pll_dat_w.storage,
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i_DEN=self._pll_read.re | self._pll_write.re,
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i_DWE=self._pll_write.re,
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o_DRDY=pll_drdy,
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i_DCLK=ClockSignal())
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@ -67,7 +67,7 @@ class Clocking(Module, AutoCSR):
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Instance("BUFG", i_I=pll_clk2, o_O=self._cd_pix.clk),
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MultiReg(locked_async, self.locked, "sys")
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]
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self.comb += self._r_locked.status.eq(self.locked)
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self.comb += self._locked.status.eq(self.locked)
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# sychronize pix+pix2x reset
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pix_rst_n = 1
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@ -7,10 +7,10 @@ class DataCapture(Module, AutoCSR):
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self.serdesstrobe = Signal()
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self.d = Signal(10)
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self._r_dly_ctl = CSR(6)
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self._r_dly_busy = CSRStatus(2)
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self._r_phase = CSRStatus(2)
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self._r_phase_reset = CSR()
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self._dly_ctl = CSR(6)
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self._dly_busy = CSRStatus(2)
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self._phase = CSRStatus(2)
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self._phase_reset = CSR()
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###
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@ -163,21 +163,21 @@ class DataCapture(Module, AutoCSR):
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]
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self.comb += [
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self.do_delay_master_cal.i.eq(self._r_dly_ctl.re & self._r_dly_ctl.r[0]),
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self.do_delay_master_rst.i.eq(self._r_dly_ctl.re & self._r_dly_ctl.r[1]),
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self.do_delay_slave_cal.i.eq(self._r_dly_ctl.re & self._r_dly_ctl.r[2]),
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self.do_delay_slave_rst.i.eq(self._r_dly_ctl.re & self._r_dly_ctl.r[3]),
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self.do_delay_inc.i.eq(self._r_dly_ctl.re & self._r_dly_ctl.r[4]),
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self.do_delay_dec.i.eq(self._r_dly_ctl.re & self._r_dly_ctl.r[5]),
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self._r_dly_busy.status.eq(Cat(sys_delay_master_pending, sys_delay_slave_pending))
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self.do_delay_master_cal.i.eq(self._dly_ctl.re & self._dly_ctl.r[0]),
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self.do_delay_master_rst.i.eq(self._dly_ctl.re & self._dly_ctl.r[1]),
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self.do_delay_slave_cal.i.eq(self._dly_ctl.re & self._dly_ctl.r[2]),
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self.do_delay_slave_rst.i.eq(self._dly_ctl.re & self._dly_ctl.r[3]),
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self.do_delay_inc.i.eq(self._dly_ctl.re & self._dly_ctl.r[4]),
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self.do_delay_dec.i.eq(self._dly_ctl.re & self._dly_ctl.r[5]),
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self._dly_busy.status.eq(Cat(sys_delay_master_pending, sys_delay_slave_pending))
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]
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# Phase detector control
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self.specials += MultiReg(Cat(too_late, too_early), self._r_phase.status)
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self.specials += MultiReg(Cat(too_late, too_early), self._phase.status)
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self.submodules.do_reset_lateness = PulseSynchronizer("sys", "pix2x")
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self.comb += [
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reset_lateness.eq(self.do_reset_lateness.o),
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self.do_reset_lateness.i.eq(self._r_phase_reset.re)
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self.do_reset_lateness.i.eq(self._phase_reset.re)
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]
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# 5:10 deserialization
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@ -15,19 +15,19 @@ class _Slot(Module, AutoCSR):
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self.address_valid = Signal()
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self.address_done = Signal()
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self._r_status = CSRStorage(2, write_from_dev=True)
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self._r_address = CSRStorage(addr_bits + alignment_bits, alignment_bits=alignment_bits, write_from_dev=True)
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self._status = CSRStorage(2, write_from_dev=True)
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self._address = CSRStorage(addr_bits + alignment_bits, alignment_bits=alignment_bits, write_from_dev=True)
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###
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self.comb += [
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self.address.eq(self._r_address.storage),
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self.address_valid.eq(self._r_status.storage[0]),
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self._r_status.dat_w.eq(2),
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self._r_status.we.eq(self.address_done),
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self._r_address.dat_w.eq(self.address_reached),
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self._r_address.we.eq(self.address_done),
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self.ev_source.trigger.eq(self._r_status.storage[1])
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self.address.eq(self._address.storage),
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self.address_valid.eq(self._status.storage[0]),
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self._status.dat_w.eq(2),
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self._status.we.eq(self.address_done),
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self._address.dat_w.eq(self.address_reached),
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self._address.we.eq(self.address_done),
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self.ev_source.trigger.eq(self._status.storage[1])
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]
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class _SlotArray(Module, AutoCSR):
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@ -66,7 +66,7 @@ class DMA(Module):
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fifo_word_width = 24*bus_dw//32
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self.frame = Sink([("sof", 1), ("pixels", fifo_word_width)])
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self._r_frame_size = CSRStorage(bus_aw + alignment_bits, alignment_bits=alignment_bits)
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self._frame_size = CSRStorage(bus_aw + alignment_bits, alignment_bits=alignment_bits)
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self.submodules._slot_array = _SlotArray(nslots, bus_aw, alignment_bits)
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self.ev = self._slot_array.ev
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@ -85,7 +85,7 @@ class DMA(Module):
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self.sync += [
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If(reset_words,
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current_address.eq(self._slot_array.address),
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mwords_remaining.eq(self._r_frame_size.storage)
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mwords_remaining.eq(self._frame_size.storage)
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).Elif(count_word,
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current_address.eq(current_address + 1),
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mwords_remaining.eq(mwords_remaining - 1)
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@ -138,4 +138,4 @@ class DMA(Module):
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)
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def get_csrs(self):
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return [self._r_frame_size] + self._slot_array.get_csrs()
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return [self._frame_size] + self._slot_array.get_csrs()
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@ -18,19 +18,19 @@ _default_edid = [
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class EDID(Module, AutoCSR):
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def __init__(self, pads, default=_default_edid):
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self._r_hpd_notif = CSRStatus()
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self._r_hpd_en = CSRStorage()
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self._hpd_notif = CSRStatus()
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self._hpd_en = CSRStorage()
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self.specials.mem = Memory(8, 128, init=default)
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###
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# HPD
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if hasattr(pads, "hpd_notif"):
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self.specials += MultiReg(pads.hpd_notif, self._r_hpd_notif.status)
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self.specials += MultiReg(pads.hpd_notif, self._hpd_notif.status)
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else:
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self.comb += self._r_hpd_notif.status.eq(1)
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self.comb += self._hpd_notif.status.eq(1)
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if hasattr(pads, "hpd_en"):
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self.comb += pads.hpd_en.eq(self._r_hpd_en.storage)
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self.comb += pads.hpd_en.eq(self._hpd_en.storage)
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# EDID
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scl_raw = Signal()
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@ -186,4 +186,4 @@ class EDID(Module, AutoCSR):
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for state in fsm.actions.keys():
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fsm.act(state, If(start, NextState("RCV_ADDRESS")))
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fsm.act(state, If(~self._r_hpd_en.storage, NextState("WAIT_START")))
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fsm.act(state, If(~self._hpd_en.storage, NextState("WAIT_START")))
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@ -8,8 +8,8 @@ from misoclib.video.dvisampler.common import control_tokens
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class WER(Module, AutoCSR):
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def __init__(self, period_bits=24):
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self.data = Signal(10)
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self._r_update = CSR()
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self._r_value = CSRStatus(period_bits)
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self._update = CSR()
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self._value = CSRStatus(period_bits)
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###
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@ -56,4 +56,4 @@ class WER(Module, AutoCSR):
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self.sync += If(self.ps_counter.o, wer_counter_sys.eq(wer_counter_r))
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# register interface
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self.sync += If(self._r_update.re, self._r_value.status.eq(wer_counter_sys))
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self.sync += If(self._update.re, self._value.status.eq(wer_counter_sys))
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