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Merge pull request #363 from antmicro/litex-sim-ddr4 

tools/litex_sim: add ddr4 PhySettings
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enjoy-digital 2020-01-28 15:36:24 +01:00 committed by GitHub
parent 0820adbda1 c02dd5e8f9
commit b4b56db4e3
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1 changed files with 13 additions and 0 deletions
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litex/tools/litex_sim.py
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@ -72,6 +72,7 @@ sdram_module_nphases = {
"LPDDR": 2,
"DDR2": 2,
"DDR3": 4,
"DDR4": 4,
}
def get_sdram_phy_settings(memtype, data_width, clk_freq):
@ -109,6 +110,18 @@ def get_sdram_phy_settings(memtype, data_width, clk_freq):
wrcmdphase, wrphase = get_sys_phases(nphases, cwl_sys_latency, cwl)
read_latency = 2 + cl_sys_latency + 2 + 3
write_latency = cwl_sys_latency
elif memtype == "DDR4":
# Settings from usddrphy
tck = 2/(2*nphases*clk_freq)
cmd_latency = 0
cl, cwl = get_cl_cw(memtype, tck)
cl_sys_latency = get_sys_latency(nphases, cl)
cwl = cwl + cmd_latency
cwl_sys_latency = get_sys_latency(nphases, cwl)
rdcmdphase, rdphase = get_sys_phases(nphases, cl_sys_latency, cl)
wrcmdphase, wrphase = get_sys_phases(nphases, cwl_sys_latency, cwl)
read_latency = 2 + cl_sys_latency + 1 + 3
write_latency = cwl_sys_latency
sdram_phy_settings = {
"nphases": nphases,