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interconnect/avalon: minor cleanup, remove max on SyncFIFO depth.

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This commit is contained in:
Florent Kermarrec 2020-07-08 07:53:42 +02:00
parent 8af4e05c7f
commit b54b3b3362
1 changed files with 7 additions and 9 deletions
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16
litex/soc/interconnect/avalon.py
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@ -1,4 +1,4 @@
# This file is Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
# This file is Copyright (c) 2019-2020 Florent Kermarrec <florent@enjoy-digital.fr>
# License: BSD
"""Avalon support for LiteX"""
@ -19,7 +19,7 @@ from litex.soc.interconnect import stream
class Native2AvalonST(Module):
"""Native LiteX's stream to Avalon-ST stream"""
def __init__(self, layout, latency=2):
self.sink = sink = stream.Endpoint(layout)
self.sink = sink = stream.Endpoint(layout)
self.source = source = stream.Endpoint(layout)
# # #
@ -38,15 +38,13 @@ class Native2AvalonST(Module):
class AvalonST2Native(Module):
"""Avalon-ST Stream to native LiteX's stream"""
def __init__(self, layout, latency=2):
self.sink = sink = stream.Endpoint(layout)
self.sink = sink = stream.Endpoint(layout)
self.source = source = stream.Endpoint(layout)
# # #
buf = stream.SyncFIFO(layout, max(latency, 4))
buf = stream.SyncFIFO(layout, latency)
self.submodules += buf
self.comb += [
sink.connect(buf.sink, omit={"ready"}),
sink.ready.eq(source.ready),
buf.source.connect(source)
]
self.comb += sink.connect(buf.sink, omit={"ready"})
self.comb += sink.ready.eq(source.ready)
self.comb += buf.source.connect(source)