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fhdl/verilog: improve error reporting

This commit is contained in:
Sebastien Bourdeauducq 2013-06-24 19:44:25 +02:00
parent d6f7b4cee6
commit b56cb3cefc
1 changed files with 2 additions and 2 deletions
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4
migen/fhdl/verilog.py
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@ -80,7 +80,7 @@ def _printexpr(ns, node):
elif isinstance(node, Replicate): elif isinstance(node, Replicate):
return "{" + str(node.n) + "{" + _printexpr(ns, node.v)[0] + "}}", False return "{" + str(node.n) + "{" + _printexpr(ns, node.v)[0] + "}}", False
else: else:
raise TypeError raise TypeError("Expression of unrecognized type: "+str(type(node)))
(_AT_BLOCKING, _AT_NONBLOCKING, _AT_SIGNAL) = range(3) (_AT_BLOCKING, _AT_NONBLOCKING, _AT_SIGNAL) = range(3)
@ -124,7 +124,7 @@ def _printnode(ns, at, level, node):
else: else:
return "" return ""
else: else:
raise TypeError raise TypeError("Node of unrecognized type: "+str(type(node)))
def _list_comb_wires(f): def _list_comb_wires(f):
r = set() r = set()