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cores/clock/ecp5: Add dynamic phase adjustment signals.

This commit is contained in:
Vegard Storheil Eriksen 2021-06-19 11:19:16 +02:00
parent e7d04a2d1b
commit b58c416a24
1 changed files with 13 additions and 0 deletions
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13
litex/soc/cores/clock/lattice_ecp5.py
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@ -32,6 +32,11 @@ class ECP5PLL(Module):
self.config = {} self.config = {}
self.params = {} self.params = {}
self.phase_sel = Signal(2)
self.phase_dir = Signal()
self.phase_step = Signal()
self.phase_load = Signal()
def register_clkin(self, clkin, freq): def register_clkin(self, clkin, freq):
(clki_freq_min, clki_freq_max) = self.clki_freq_range (clki_freq_min, clki_freq_max) = self.clki_freq_range
assert freq >= clki_freq_min assert freq >= clki_freq_min
@ -108,6 +113,14 @@ class ECP5PLL(Module):
p_CLKOS3_CPHASE = 23, p_CLKOS3_CPHASE = 23,
p_CLKFB_DIV = config["clkfb_div"], p_CLKFB_DIV = config["clkfb_div"],
p_CLKI_DIV = config["clki_div"], p_CLKI_DIV = config["clki_div"],
p_DPHASE_SOURCE = "ENABLED",
i_PHASESEL0 = self.phase_sel[0],
i_PHASESEL1 = self.phase_sel[1],
i_PHASEDIR = self.phase_dir,
i_PHASESTEP = self.phase_step,
i_PHASELOADREG = self.phase_load,
) )
self.comb += self.locked.eq(locked & ~self.reset) self.comb += self.locked.eq(locked & ~self.reset)
for n, (clk, f, p, m) in sorted(self.clkouts.items()): for n, (clk, f, p, m) in sorted(self.clkouts.items()):