sram: fix WE signal

This commit is contained in:
Sebastien Bourdeauducq 2012-02-03 10:38:17 +01:00
parent 8a2646a549
commit b5cb1083ab
1 changed files with 1 additions and 1 deletions

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@ -9,7 +9,7 @@ class SRAM:
def get_fragment(self):
# generate write enable signal
we = Signal(BV(4))
comb = [we[i].eq(self.bus.cyc_i & self.bus.stb_i & self.bus.sel_i[3-i])
comb = [we[i].eq(self.bus.cyc_i & self.bus.stb_i & self.bus.we_i & self.bus.sel_i[3-i])
for i in range(4)]
# split address
nbits = bits_for(self.depth-1)