Hardware/litex
1
0
Fork 0
mirror of https://github.com/enjoy-digital/litex.git synced 2025-01-04 09:52:26 -05:00
Code Issues Projects Releases Packages Wiki Activity

sram: fix WE signal

Browse source
This commit is contained in:
Sebastien Bourdeauducq 2012-02-03 10:38:17 +01:00
parent 8a2646a549
commit b5cb1083ab
1 changed files with 1 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
milkymist/sram/__init__.py
View file

@ -9,7 +9,7 @@ class SRAM:
def get_fragment(self): def get_fragment(self):
# generate write enable signal # generate write enable signal
we = Signal(BV(4)) we = Signal(BV(4))
comb = [we[i].eq(self.bus.cyc_i & self.bus.stb_i & self.bus.sel_i[3-i]) comb = [we[i].eq(self.bus.cyc_i & self.bus.stb_i & self.bus.we_i & self.bus.sel_i[3-i])
for i in range(4)] for i in range(4)]
# split address # split address
nbits = bits_for(self.depth-1) nbits = bits_for(self.depth-1)