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build/efinix/common: Update EfinixSDRInputImpl and minor cleanup.

This commit is contained in:
Florent Kermarrec 2024-09-26 11:50:37 +02:00
parent 0e337e2079
commit b5e91473b7
1 changed files with 5 additions and 11 deletions
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16
litex/build/efinix/common.py
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@ -105,7 +105,7 @@ class EfinixClkInput(Module):
def lower(dr): def lower(dr):
return EfinixClkInputImpl(dr.platform, dr.i, dr.o) return EfinixClkInputImpl(dr.platform, dr.i, dr.o)
# Efinix Clk Output --------------------------------------------------------------------------------- # Efinix Clk Output --------------------------------------------------------------------------------
class EfinixClkOutputImpl(Module): class EfinixClkOutputImpl(Module):
def __init__(self, platform, i, o): def __init__(self, platform, i, o):
@ -160,8 +160,6 @@ class EfinixTristate(Module):
def lower(dr): def lower(dr):
return EfinixTristateImpl(dr.platform, dr.target, dr.o, dr.oe, dr.i) return EfinixTristateImpl(dr.platform, dr.target, dr.o, dr.oe, dr.i)
# Efinix DifferentialOutput ------------------------------------------------------------------------ # Efinix DifferentialOutput ------------------------------------------------------------------------
class EfinixDifferentialOutputImpl(Module): class EfinixDifferentialOutputImpl(Module):
@ -265,11 +263,7 @@ class EfinixDifferentialInput:
def lower(dr): def lower(dr):
return EfinixDifferentialInputImpl(dr.platform, dr.i_p, dr.i_n, dr.o) return EfinixDifferentialInputImpl(dr.platform, dr.i_p, dr.i_n, dr.o)
# Efinix DDRTristate -------------------------------------------------------------------------------
# Efinix DDRTristate ---------------------------------------------------------------------------------
class EfinixDDRTristateImpl(Module): class EfinixDDRTristateImpl(Module):
def __init__(self, platform, io, o1, o2, oe1, oe2, i1, i2, clk): def __init__(self, platform, io, o1, o2, oe1, oe2, i1, i2, clk):
@ -351,7 +345,7 @@ class EfinixSDRTristate(Module):
def lower(dr): def lower(dr):
return EfinixSDRTristateImpl(dr.platform, dr.io, dr.o, dr.oe, dr.i, dr.clk) return EfinixSDRTristateImpl(dr.platform, dr.io, dr.o, dr.oe, dr.i, dr.clk)
# Efinix SDROutput ------------------------------------------------------------------------------- # Efinix SDROutput ---------------------------------------------------------------------------------
class EfinixSDROutputImpl(Module): class EfinixSDROutputImpl(Module):
def __init__(self, platform, i, o, clk): def __init__(self, platform, i, o, clk):
@ -383,7 +377,6 @@ class EfinixSDROutput(Module):
def lower(dr): def lower(dr):
return EfinixSDROutputImpl(dr.platform, dr.i, dr.o, dr.clk) return EfinixSDROutputImpl(dr.platform, dr.i, dr.o, dr.clk)
# Efinix DDROutput --------------------------------------------------------------------------------- # Efinix DDROutput ---------------------------------------------------------------------------------
class EfinixDDROutputImpl(Module): class EfinixDDROutputImpl(Module):
@ -421,6 +414,7 @@ class EfinixDDROutput:
class EfinixSDRInputImpl(Module): class EfinixSDRInputImpl(Module):
def __init__(self, platform, i, o, clk): def __init__(self, platform, i, o, clk):
assert_is_signal_or_clocksignal(clk)
io_name = platform.get_pin_name(i) io_name = platform.get_pin_name(i)
io_pad = platform.get_pin_location(i) io_pad = platform.get_pin_location(i)
io_prop = platform.get_pin_properties(i) io_prop = platform.get_pin_properties(i)
@ -434,7 +428,7 @@ class EfinixSDRInputImpl(Module):
"properties" : io_prop, "properties" : io_prop,
"size" : 1, "size" : 1,
"in_reg" : "REG", "in_reg" : "REG",
"in_clk_pin" : clk.name_override, # FIXME. "in_clk_pin" : clk,
"in_clk_inv" : 0 "in_clk_inv" : 0
} }
platform.toolchain.ifacewriter.blocks.append(block) platform.toolchain.ifacewriter.blocks.append(block)